[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

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@@ -152,7 +118,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
       continue;
     if (!UseMO.getReg().isVirtual())
       continue;
-    if (!isVectorRegClass(UseMO.getReg()))
+    if (!TII->isVectorRegClass(MRI->getRegClass(UseMO.getReg())))
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ostannard wrote:

Why does it matter if this is a vector register? Could this not also apply to any other register class with an early-clobber constraint? It might be that RISC-V had this constraint on it's vector instructions/registers, but we should change this name to describe that actual condition for the target-independent version.

I also don't see any checks here for the early-clobber constraint, should that be checked here?

https://github.com/llvm/llvm-project/pull/77770