[llvm] [AMDGPU] New llvm.amdgcn.wave.id intrinsic (PR #79325)

[Matt Arsenault via llvm-commits]

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@@ -7920,6 +7920,18 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
   return Loads[0];
 }
 
+SDValue SITargetLowering::lowerWaveID(SelectionDAG &DAG, SDValue Op) const {
+  // With architected SGPRs, waveIDinGroup is in TTMP8[29:25].
+  if (!Subtarget->hasArchitectedSGPRs())
+    return {};
+  SDLoc SL(Op);
+  MVT VT = MVT::i32;
+  SDValue TTMP8 = CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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arsenm wrote:

I assume these registers are reserved? In which case you don't need to bother adding them to live ins 

https://github.com/llvm/llvm-project/pull/79325