[llvm] [RISCV] Re-format RISCVFeatures.td so it doesn't look like AssemblerPredicate is an operand to Predicate. (PR #79076)

Wang Pengcheng via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 23 01:17:45 PST 2024

Previous message: [llvm] [AArch64][GlobalISel] More FCmp legalization. (PR #78734)
Next message: [llvm] [RISCV] Re-format RISCVFeatures.td so it doesn't look like AssemblerPredicate is an operand to Predicate. (PR #79076)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/79076

Previous message: [llvm] [AArch64][GlobalISel] More FCmp legalization. (PR #78734)
Next message: [llvm] [RISCV] Re-format RISCVFeatures.td so it doesn't look like AssemblerPredicate is an operand to Predicate. (PR #79076)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list