[llvm] [AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (PR #71485)

[via llvm-commits]

================
@@ -1504,11 +1513,37 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
     // Verify alignment is legal, so we don't create relocations
     // that can't be supported.
     unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+    // For non-TOC-based local-exec TLS accesses with non-zero offsets, the
+    // machine operand (which is a TargetGlobalTLSAddress) is expected to be
+    // the same operand for both loads and stores.
+    for (const MachineOperand &TempMO : MI->operands()) {
+      if (((TempMO.getTargetFlags() == PPCII::MO_TPREL_FLAG)) &&
+          TempMO.getOperandNo() == 1)
+        OpNum = 1;
+    }
     const MachineOperand &MO = MI->getOperand(OpNum);
     if (MO.isGlobal()) {
       const DataLayout &DL = MO.getGlobal()->getParent()->getDataLayout();
       if (MO.getGlobal()->getPointerAlignment(DL) < 4)
         llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+
+      // A faster non-TOC-based local-exec sequence is represented by
+      // directly loading or storing off of the thread pointer and with
+      // an immediate operand having the MO_TPREL_FLAG.
+      // Such instructions do not otherwise arise.
+      unsigned Flag = MO.getTargetFlags();
+      if (Flag == PPCII::MO_TPREL_FLAG) {
+        assert(HasAIXSmallLocalExecTLS &&
+               "loads/stores with thread-pointer only expected with "
+               "local-exec small TLS");
+        int64_t Offset = MO.getOffset();
+        LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
+        const MCExpr *Expr = getAdjustedLocalExecExpr(MO, Offset);
+        if (Expr)
+          TmpInst.getOperand(OpNum) = MCOperand::createExpr(Expr);
+        EmitToStreamer(*OutStreamer, TmpInst);
+        return;
----------------
diggerlin wrote:

most of the code are same as line 1580~1599, we can simple the code as keeping special code: 

 ```
 case PPC::LD:
  case PPC::STD:
  case PPC::LWA_32:
  case PPC::LWA: {
const MachineOperand &MO = MI->getOperand(OpNum);
    if (MO.isGlobal()) {
      const DataLayout &DL = MO.getGlobal()->getParent()->getDataLayout();
      if (MO.getGlobal()->getPointerAlignment(DL) < 4)
        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
        }
      
case PPC::LBZ:
case PPC::LBZ8:
...
```


is it possible?

https://github.com/llvm/llvm-project/pull/71485