[llvm] [RISCV] Add regalloc hints for Zcb instructions. (PR #78949)

[Yingwei Zheng via llvm-commits]

================
@@ -789,9 +790,16 @@ bool RISCVRegisterInfo::getRegAllocationHints(
     case RISCV::SUBW:
       NeedGPRC = true;
       return true;
-    case RISCV::ANDI:
+    case RISCV::ANDI: {
       NeedGPRC = true;
-      return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm());
+      if (!MI.getOperand(2).isImm())
+        return false;
+      int64_t Imm = MI.getOperand(2).getImm();
+      if (isInt<6>(Imm))
+        return true;
+      // c.zext.h
----------------
dtcxzyw wrote:

```suggestion
      // c.zext.b
```

https://github.com/llvm/llvm-project/pull/78949