[llvm] [RISCV] Add regalloc hints for Zcb instructions. (PR #78949)

[Yingwei Zheng via llvm-commits]

================
@@ -802,6 +810,23 @@ bool RISCVRegisterInfo::getRegAllocationHints(
     case RISCV::ADDI:
     case RISCV::ADDIW:
       return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm());
+    case RISCV::MUL:
+    case RISCV::SEXT_B:
+    case RISCV::SEXT_H:
+    case RISCV::ZEXT_H_RV32:
+    case RISCV::ZEXT_H_RV64:
+      // c.mul, c.sext.b, c.sext.h, c.zext.h
+      NeedGPRC = true;
+      return Subtarget.hasStdExtZcb();
+    case RISCV::ADD_UW:
+      // c.zext.w
+      NeedGPRC = true;
+      return Subtarget.hasStdExtZcb() && MI.getOperand(2).getReg() == RISCV::X0;
----------------
dtcxzyw wrote:

```suggestion
      return Subtarget.hasStdExtZcb() && MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0;
```


https://github.com/llvm/llvm-project/pull/78949