[llvm] [RISCV][ISel] Remove redundant vmerge for the vwadd. (PR #78403)

[Craig Topper via llvm-commits]

================
@@ -13457,6 +13457,56 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   return InputRootReplacement;
 }
 
+// (vwadd y, (select cond, x, 0)) -> select cond (vwadd y, x), y
+static SDValue combineVWADDSelect(SDNode *N, SelectionDAG &DAG) {
+  unsigned Opc = N->getOpcode();
+  assert(Opc == RISCVISD::VWADD_VL || Opc == RISCVISD::VWADDU_VL ||
+         Opc == RISCVISD::VWADD_W_VL || Opc == RISCVISD::VWADDU_W_VL);
+
+  SDValue Merge = N->getOperand(1);
+  unsigned MergeID = 1;
+
+  if (Merge.getOpcode() != RISCVISD::VMERGE_VL) {
+    Merge = N->getOperand(0);
+    MergeID = 0;
+  }
+
+  if (Merge.getOpcode() != RISCVISD::VMERGE_VL)
+    return SDValue();
+
+  SDValue Cond = Merge->getOperand(0);
+  SDValue X = Merge->getOperand(1);
+  SDValue Z = Merge->getOperand(2);
+
+  if (Z.getOpcode() != ISD::INSERT_SUBVECTOR ||
+      !ISD::isBuildVectorAllZeros(Z.getOperand(1).getNode()))
+    return SDValue();
+
+  if (!Merge.hasOneUse())
+    return SDValue();
+
+  SmallVector<SDValue, 6> Ops(N->op_values());
----------------
topperc wrote:

Why 6? I think there are only 5 operands. LHS, RHS, Passthru, Mask, VL

https://github.com/llvm/llvm-project/pull/78403