[llvm] [RISCV][ISel] Remove redundant vmerge for the vwadd. (PR #78403)

[Craig Topper via llvm-commits]

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@@ -13457,6 +13457,56 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   return InputRootReplacement;
 }
 
+// (vwadd y, (select cond, x, 0)) -> select cond (vwadd y, x), y
+static SDValue combineVWADDSelect(SDNode *N, SelectionDAG &DAG) {
+  unsigned Opc = N->getOpcode();
+  assert(Opc == RISCVISD::VWADD_VL || Opc == RISCVISD::VWADDU_VL ||
+         Opc == RISCVISD::VWADD_W_VL || Opc == RISCVISD::VWADDU_W_VL);
+
+  SDValue Merge = N->getOperand(1);
+  unsigned MergeID = 1;
+
+  if (Merge.getOpcode() != RISCVISD::VMERGE_VL) {
+    Merge = N->getOperand(0);
+    MergeID = 0;
+  }
+
+  if (Merge.getOpcode() != RISCVISD::VMERGE_VL)
+    return SDValue();
+
+  SDValue Cond = Merge->getOperand(0);
+  SDValue X = Merge->getOperand(1);
+  SDValue Z = Merge->getOperand(2);
+
+  if (Z.getOpcode() != ISD::INSERT_SUBVECTOR ||
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topperc wrote:

This doesn't check what operand 0 of the insert is or the size of the insertion. So you only know some subvector of the input is 0. You don't know the whole vector is 0.

https://github.com/llvm/llvm-project/pull/78403