[llvm] [RISCV] Add IntrArgMemOnly for vector load/store intrinsic (PR #78415)

[Jianjian Guan via llvm-commits]

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@@ -200,7 +203,8 @@ let TargetPrefix = "riscv" in {
         : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_ptr_ty,
                      llvm_anyint_ty, LLVMMatchType<1>],
-                    [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
+                    [NoCapture<ArgIndex<1>>, IntrReadMem, IntrArgMemOnly]>,
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jacquesguan wrote:

Your commit makes sense. I still don't understand the comment of `IntrArgMemOnly` well, it says: "but may access an unspecified amount", it seems allow to let the intrinsic access more memory.

https://github.com/llvm/llvm-project/pull/78415