[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -1480,6 +1480,11 @@ static bool IsSVECalleeSave(MachineBasicBlock::iterator I) {
   switch (I->getOpcode()) {
   default:
     return false;
+  case AArch64::PTRUE_C_B:
+  case AArch64::LD1B_2Z_IMM:
+  case AArch64::ST1B_2Z_IMM:
+    return I->getMF()->getSubtarget<AArch64Subtarget>().hasSVE2p1() ||
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momchil-velikov wrote:

If we are not generating code for these targets, we shouldn't be emitting those instructions in the first place.

https://github.com/llvm/llvm-project/pull/77665