[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 03:27:12 PST 2024
================
@@ -970,6 +970,9 @@ def FeatureFastUnalignedAccess
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
+def FeatureNoRAS : SubtargetFeature<"no-ras", "HasRAS", "false",
+ "Hasn't RAS (Return Address Stack)">;
+
----------------
dtcxzyw wrote:
https://github.com/llvm/llvm-project/blob/8f7fdd94ef19af7b4905b316c253a78219a6038f/llvm/lib/Target/ARM/ARM.td#L418-L422
Not sure which one is better.
https://github.com/llvm/llvm-project/pull/78417
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