[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Michael Maitland via llvm-commits]

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@@ -36,6 +36,7 @@ include "GISel/RISCVRegisterBanks.td"
 
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
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michaelmaitland wrote:

I am currently exploring some refactors of the scheduler model in our downstream for better code reusability. I will take a look to see if what you suggest is possible. I see your point about the llvm-mca reporting. But besides llvm-mca, the suggested change doesn't impact scheduling. In my experience, the relevant TblGen classes may make this change harder than it is worth. 

https://github.com/llvm/llvm-project/pull/77989