[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Wang Pengcheng via llvm-commits]

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@@ -36,6 +36,7 @@ include "GISel/RISCVRegisterBanks.td"
 
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
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wangpc-pp wrote:

OK, I may use the wrong words here. I meant that the CPU resources/pipeline are different, X280 has additional vector pipeline. Intuitively, they should be separated (I think). And, the outputs of `llvm-mca` contain vector resources even for scalar CPU like `sifive-u74`.

https://github.com/llvm/llvm-project/pull/77989