[llvm] [MacroFusion][RISCV] Allocate same register for second instruction of fusible pair (PR #77461)

[Craig Topper via llvm-commits]

================
@@ -114,6 +114,7 @@ class MachineInstr
                              // this instruction.
     Unpredictable = 1 << 16, // Instruction with unpredictable condition.
     NoConvergent = 1 << 17,  // Call does not require convergence guarantees.
+    Fusible = 1 << 18,       // Instruction is the second of a fusible pair.
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topperc wrote:

>From the RISC-V section of this page https://en.wikichip.org/wiki/macro-operation_fusion which are also listed here https://xiangshan-doc.readthedocs.io/zh-cn/latest/frontend/decode/

```
slli rd, rs1, {1,2,3}
add rd, rd, rs2
```

There are a few others on https://xiangshan-doc.readthedocs.io/zh-cn/latest/frontend/decode/




https://github.com/llvm/llvm-project/pull/77461