[llvm] [MacroFusion][RISCV] Allocate same register for second instruction of fusible pair (PR #77461)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 22:52:21 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/77461
>From 509549381b86e0059bc0af7aec7407b33b3fc3d8 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 9 Jan 2024 20:53:18 +0800
Subject: [PATCH 1/3] [MacroFusion][RISCV] Allocate same register for second
instruction of fusible pair
We add a MI flag to indicate the constraint and set this flag to
true for the second instruction of fusible pairs in pre-regalloc
macrofusion.
Then, we add register allocation hints for it.
During regalloc, the allocator will choose the same register
according to the hint.
This is a PoC currently.
---
llvm/include/llvm/CodeGen/MachineInstr.h | 4 +++
llvm/lib/CodeGen/MacroFusion.cpp | 1 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 ++
llvm/test/CodeGen/RISCV/pr76779.ll | 37 +++++++++++++++++++++
4 files changed, 44 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/pr76779.ll
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index bd72ac23fc9c08..f694c27a3f7f7f 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -114,6 +114,7 @@ class MachineInstr
// this instruction.
Unpredictable = 1 << 16, // Instruction with unpredictable condition.
NoConvergent = 1 << 17, // Call does not require convergence guarantees.
+ Fusible = 1 << 18, // Instruction is the second of a fusible pair.
};
private:
@@ -1030,6 +1031,9 @@ class MachineInstr
return hasProperty(MCID::Convergent, Type);
}
+ /// Return true if this instruction is fusible.
+ bool isFusible() const { return getFlag(Fusible); }
+
/// Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot(QueryType Type = AnyInBundle) const {
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index 5bd6ca0978a4b1..ce1bf9d6597ae0 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -128,6 +128,7 @@ bool llvm::fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
}
}
+ SecondSU.getInstr()->setFlag(MachineInstr::Fusible);
++NumFused;
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 24f8d600f1eafc..741bb51d069437 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -823,6 +823,8 @@ bool RISCVRegisterInfo::getRegAllocationHints(
tryAddHint(MO, MI.getOperand(0), NeedGPRC);
}
}
+ if (MI.isFusible() && OpIdx == 1)
+ tryAddHint(MO, MI.getOperand(0), false);
}
for (MCPhysReg OrderReg : Order)
diff --git a/llvm/test/CodeGen/RISCV/pr76779.ll b/llvm/test/CodeGen/RISCV/pr76779.ll
new file mode 100644
index 00000000000000..cec132251e3c4c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr76779.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -mtriple=riscv64 -mattr=+f -target-abi=lp64f \
+;RUN: | FileCheck %s --check-prefix=NOFUSION
+;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion \
+;RUN: -target-abi=lp64f | FileCheck %s --check-prefix=FUSION
+;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler \
+;RUN: -target-abi=lp64f | FileCheck %s --check-prefixes=FUSION-POSTRA
+
+define void @foo(i32 noundef signext %0, i32 noundef signext %1) {
+; NOFUSION-LABEL: foo:
+; NOFUSION: # %bb.0:
+; NOFUSION-NEXT: lui a0, 3014
+; NOFUSION-NEXT: addiw a2, a0, 334
+; NOFUSION-NEXT: mv a0, a1
+; NOFUSION-NEXT: mv a1, a2
+; NOFUSION-NEXT: tail bar
+;
+; FUSION-LABEL: foo:
+; FUSION: # %bb.0:
+; FUSION-NEXT: lui a2, 3014
+; FUSION-NEXT: addiw a2, a2, 334
+; FUSION-NEXT: mv a0, a1
+; FUSION-NEXT: mv a1, a2
+; FUSION-NEXT: tail bar
+;
+; FUSION-POSTRA-LABEL: foo:
+; FUSION-POSTRA: # %bb.0:
+; FUSION-POSTRA-NEXT: lui a2, 3014
+; FUSION-POSTRA-NEXT: addiw a2, a2, 334
+; FUSION-POSTRA-NEXT: mv a0, a1
+; FUSION-POSTRA-NEXT: mv a1, a2
+; FUSION-POSTRA-NEXT: tail bar
+ tail call void @bar(i32 noundef signext %1, i32 noundef signext 12345678)
+ ret void
+}
+
+declare void @bar(i32 noundef signext, i32 noundef signext)
>From e467c5c8744fa3a8ee1a197816c9ec451b062f17 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 11 Jan 2024 14:26:54 +0800
Subject: [PATCH 2/3] Set MIFlag only in pre-ra
---
llvm/lib/CodeGen/MacroFusion.cpp | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index ce1bf9d6597ae0..e4aa4636442db2 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -13,6 +13,7 @@
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
@@ -128,7 +129,12 @@ bool llvm::fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
}
}
- SecondSU.getInstr()->setFlag(MachineInstr::Fusible);
+ // Mark the second instruction of fusible pair as MachineInstr::Fusible if
+ // this mutation is running in pre-ra scheduler.
+ if (!DAG.MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::NoVRegs))
+ SecondSU.getInstr()->setFlag(MachineInstr::Fusible);
+
++NumFused;
return true;
}
>From 04557095cc8906f005d7d96c35b4216f4c62f9a8 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 11 Jan 2024 14:52:09 +0800
Subject: [PATCH 3/3] Clean includes
---
llvm/lib/CodeGen/MacroFusion.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index e4aa4636442db2..3efae951dba53e 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -13,7 +13,6 @@
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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