[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

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``````````bash
git-clang-format --diff 1d5106d69cf475215887c42834158d710e586f1b 75c621bd18667664a4263ab4e81d169be0563614 -- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 7a332bfd18..0a1fc46e64 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3100,9 +3100,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
     if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
       MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
       if (RPI.isPaired())
-         MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
+        MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
     }
-
   }
   return true;
 }
@@ -3139,30 +3138,30 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
     Align Alignment;
     switch (RPI.Type) {
     case RegPairInfo::GPR:
-       LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
-       Size = 8;
-       Alignment = Align(8);
-       break;
+      LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
+      Size = 8;
+      Alignment = Align(8);
+      break;
     case RegPairInfo::FPR64:
-       LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
-       Size = 8;
-       Alignment = Align(8);
-       break;
+      LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
+      Size = 8;
+      Alignment = Align(8);
+      break;
     case RegPairInfo::FPR128:
-       LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
-       Size = 16;
-       Alignment = Align(16);
-       break;
+      LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
+      Size = 16;
+      Alignment = Align(16);
+      break;
     case RegPairInfo::ZPR:
-       LdrOpc = RPI.isPaired() ? AArch64::LD1B_2Z_IMM : AArch64::LDR_ZXI;
-       Size = 16;
-       Alignment = Align(16);
-       break;
+      LdrOpc = RPI.isPaired() ? AArch64::LD1B_2Z_IMM : AArch64::LDR_ZXI;
+      Size = 16;
+      Alignment = Align(16);
+      break;
     case RegPairInfo::PPR:
-       LdrOpc = AArch64::LDR_PXI;
-       Size = 2;
-       Alignment = Align(2);
-       break;
+      LdrOpc = AArch64::LDR_PXI;
+      Size = 2;
+      Alignment = Align(2);
+      break;
     }
     LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
                if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);

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https://github.com/llvm/llvm-project/pull/77665