[llvm] [AArch64] MI Scheduler: create more LDP/STP pairs (PR #77565)

[Sjoerd Meijer via llvm-commits]

sjoerdmeijer wrote:

> > We can't combine the the load in line [5] into the load on [1]: register q1 is
> > used in between.
> 
> Just because the register is used in between doesn't necessarily prevent AArch64LoadStoreOptimizer.cpp from combining loads/stores I think, it supports renaming registers in some cases when a different register can be picked.

Yes, exactly @fhahn , but not for this case (that's why in the description I mentioned the latest change in that area: https://github.com/llvm/llvm-project/pull/71908). This example has another def in between the pair, and that completely eliminates the pair from being candidates. Any renaming is considered only when this requirement of no writes in between between has been satisfied here:

https://github.com/llvm/llvm-project/blob/9e5a77f252badfc932d1e28ee998746072ddc33f/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp#L1900

That's where renaming is considered, just above that you'll see the checks. 
The compromise that I also mentioned in the description is exactly about this: doing major surgery in this area, or just adding this case here in the MI Scheduler hook.

> I think this sounds OK to go along with the other opcodes already handled. I presume that if it got this far that benchmarks looked OK too?

@davemgreen: This has been benchmarked, yes, giving improvements. I will run some more to double check, and report back soon.

> Can you split the debug messages out into a separate pr. I think they look if you wanted to just push them directly, but they should probably be committed separately.

Yeah, sorry, that's my Github inexperience, I thought they could be separately committed, but that doesn't seem to be case (they need to be squashed), so will separate that out.




https://github.com/llvm/llvm-project/pull/77565