[llvm] fb72a44 - [X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-08T19:50:28+08:00
New Revision: fb72a445c1abb21034dc4a63b8489f39150a5566

URL: https://github.com/llvm/llvm-project/commit/fb72a445c1abb21034dc4a63b8489f39150a5566
DIFF: https://github.com/llvm/llvm-project/commit/fb72a445c1abb21034dc4a63b8489f39150a5566.diff

LOG: [X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI

This patch is a straightfoward change based on the design in #77202.
It does not have any effect since we haven't supported compressing ND
to non-ND in X86CompressEVEX.cpp.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86CompressEVEX.cpp
    llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index b5928b93ffffdb..b95baddd9dea96 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -221,21 +221,27 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
 }
 
 static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
-  const MCInstrDesc &Desc = MI.getDesc();
+  uint64_t TSFlags = MI.getDesc().TSFlags;
 
   // Check for EVEX instructions only.
-  if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
+  if ((TSFlags & X86II::EncodingMask) != X86II::EVEX)
     return false;
 
-  // Check for EVEX instructions with mask or broadcast as in these cases
-  // the EVEX prefix is needed in order to carry this information
-  // thus preventing the transformation to VEX encoding.
-  if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
+  // Instructions with mask or 512-bit vector can't be converted to VEX.
+  if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2))
     return false;
 
-  // Check for EVEX instructions with L2 set. These instructions are 512-bits
-  // and can't be converted to VEX.
-  if (Desc.TSFlags & X86II::EVEX_L2)
+  // EVEX_B has several meanings.
+  // AVX512:
+  //  register form: rounding control or SAE
+  //  memory form: broadcast
+  //
+  // APX:
+  //  MAP4: NDD
+  //
+  // For AVX512 cases, EVEX prefix is needed in order to carry this information
+  // thus preventing the transformation to VEX encoding.
+  if (TSFlags & X86II::EVEX_B)
     return false;
 
   ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
@@ -245,11 +251,8 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   if (I == Table.end() || I->OldOpc != Opc)
     return false;
 
-  if (usesExtendedRegister(MI))
-    return false;
-  if (!checkVEXInstPredicate(Opc, ST))
-    return false;
-  if (!performCustomAdjustments(MI, I->NewOpc))
+  if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) ||
+      !performCustomAdjustments(MI, I->NewOpc))
     return false;
 
   const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc);
@@ -272,7 +275,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) {
   }
 #endif
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
-  if (!ST.hasAVX512() && !ST.hasEGPR())
+  if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD())
     return false;
 
   bool Changed = false;

diff  --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
index 8366d044eb3710..aa8527e75380c5 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
@@ -135,10 +135,10 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
 
   for (const CodeGenInstruction *Inst : NumberedInstructions) {
     const Record *Rec = Inst->TheDef;
+    StringRef Name = Rec->getName();
     // _REV instruction should not appear before encoding optimization
     if (!Rec->isSubClassOf("X86Inst") ||
-        Rec->getValueAsBit("isAsmParserOnly") ||
-        Rec->getName().ends_with("_REV"))
+        Rec->getValueAsBit("isAsmParserOnly") || Name.ends_with("_REV"))
       continue;
 
     // Promoted legacy instruction is in EVEX space, and has REX2-encoding
@@ -149,18 +149,19 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
             X86Local::ExplicitEVEX)
       continue;
 
-    if (NoCompressSet.find(Rec->getName()) != NoCompressSet.end())
+    if (NoCompressSet.find(Name) != NoCompressSet.end())
       continue;
 
     RecognizableInstrBase RI(*Inst);
 
+    bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
     // Add VEX encoded instructions to one of CompressedInsts vectors according
     // to it's opcode.
     if (RI.Encoding == X86Local::VEX)
       CompressedInsts[RI.Opcode].push_back(Inst);
     // Add relevant EVEX encoded instructions to PreCompressionInsts
-    else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_B &&
-             !RI.HasEVEX_L2)
+    else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
+             (!RI.HasEVEX_B || IsND))
       PreCompressionInsts.push_back(Inst);
   }
 
@@ -176,6 +177,12 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
     } else if (Name.ends_with("_EVEX")) {
       if (auto *NewRec = Records.getDef(Name.drop_back(5)))
         NewInst = &Target.getInstruction(NewRec);
+    } else if (Name.ends_with("_ND")) {
+      if (auto *NewRec = Records.getDef(Name.drop_back(3))) {
+        auto &TempInst = Target.getInstruction(NewRec);
+        if (isRegisterOperand(TempInst.Operands[0].Rec))
+          NewInst = &TempInst;
+      }
     } else {
       // For each pre-compression instruction look for a match in the appropriate
       // vector (instructions with the same opcode) using function object