[llvm] e35c912 - [RISCV][NFC] Fix gcc -Wparentheses warning in RISCVISelDAGToDAG.cpp

[Liao Chunyu via llvm-commits]

Author: Liao Chunyu
Date: 2024-01-08T06:43:32-05:00
New Revision: e35c912039a644a2cc44cf88f451f7a2cdc455d9

URL: https://github.com/llvm/llvm-project/commit/e35c912039a644a2cc44cf88f451f7a2cdc455d9
DIFF: https://github.com/llvm/llvm-project/commit/e35c912039a644a2cc44cf88f451f7a2cdc455d9.diff

LOG: [RISCV][NFC] Fix gcc -Wparentheses warning in RISCVISelDAGToDAG.cpp
warning:
RISCVISelDAGToDAG.cpp:767: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
  767 |          AM == ISD::POST_INC && "Unexpected addressing mode");

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 7257c2e8fe1f69..0d8688ba2eaeaf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -763,8 +763,8 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
     return false;
 
   EVT LoadVT = Ld->getMemoryVT();
-  assert(AM == ISD::PRE_INC ||
-         AM == ISD::POST_INC && "Unexpected addressing mode");
+  assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) &&
+         "Unexpected addressing mode");
   bool IsPre = AM == ISD::PRE_INC;
   bool IsPost = AM == ISD::POST_INC;
   int64_t Offset = C->getSExtValue();