[llvm] [PowerPC] Make verifier happy when lowering `llvm.trap` (PR #77266)

[Kai Luo via llvm-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77266

>From e4785ce7d373a50206760bf3552a3c441fdca53f Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sat, 6 Jan 2024 22:38:38 +0800
Subject: [PATCH 1/3] Use isTrap

---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..2f5352568c3ba5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
                           "stwat $RST, $RA, $RB", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTrap = 1, isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),

>From 4ad378a4c49fdbc5cbfe3145c69b23bccaa630ae Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sun, 7 Jan 2024 20:10:52 +0800
Subject: [PATCH 2/3] Up

---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 2f5352568c3ba5..bf756e39bd5d07 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
                           "stwat $RST, $RA, $RB", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTrap = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTrap = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),

>From 07de221bef48d98dfa154c67084b1948fc94fc4c Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Mon, 8 Jan 2024 11:24:24 +0800
Subject: [PATCH 3/3] Update test

---
 llvm/test/CodeGen/PowerPC/intrinsic-trap.ll | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
index b02eb5d8fd27a7..b8eb7a35f61e17 100644
--- a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
+++ b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
@@ -1,8 +1,14 @@
-; REQUIRES: asserts
-; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-- < %s 2>&1 | FileCheck %s
-; CHECK: Bad machine code: Non-terminator instruction after the first terminator
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -ppc-opt-conditional-trap \
+; RUN:   < %s | FileCheck %s
 
 define i32 @test() {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    blr
   call void @llvm.trap()
   ret i32 0
 }