[llvm] [PowerPC] Make verifier happy when lowering `llvm.trap` (PR #77266)

[Kai Luo via llvm-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/77266

`llvm.trap` is lowered to `PPC::TRAP` and `PPC::TRAP` is set as terminator. Verifier complains about terminator should not lie in the middle of an MBB. See #77095.

Fix it by removing `isTerminator` and `isBarrier` and then set `isTrap` which was introduced by https://reviews.llvm.org/D48836# and is being used by X86 and AArch64.

`PPC::TRAP` is not a hardware memory barrier and `llvm.trap` doesn't indicate a memory barrier either.

>From e4785ce7d373a50206760bf3552a3c441fdca53f Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sat, 6 Jan 2024 22:38:38 +0800
Subject: [PATCH 1/2] Use isTrap

---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..2f5352568c3ba5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
                           "stwat $RST, $RA, $RB", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTrap = 1, isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),

>From 4ad378a4c49fdbc5cbfe3145c69b23bccaa630ae Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sun, 7 Jan 2024 20:10:52 +0800
Subject: [PATCH 2/2] Up

---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 2f5352568c3ba5..bf756e39bd5d07 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
                           "stwat $RST, $RA, $RB", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTrap = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTrap = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),