[llvm] [RISCV] Refactor subreg indices. (PR #77173)

[Jessica Clarke via llvm-commits]

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@@ -63,7 +63,8 @@ def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
 def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
 def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 
-def sub_32_hi  : SubRegIndex<32, 32>;
+def sub_gpr_even : SubRegIndex<32>;
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jrtc27 wrote:

I mean, this is wrong now, right? It's not at offset 0 within the concatenated register pair, it's at offset 32? The only other valid value would be an explicit -1, but not the default of 0. Won't that make sub-register liveness break?

https://github.com/llvm/llvm-project/pull/77173