[llvm] [RISCV] Refactor subreg indices. (PR #77173)

[Jessica Clarke via llvm-commits]

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@@ -28,21 +28,21 @@ class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
   let AltNames = alt;
 }
 
-def sub_16 : SubRegIndex<16>;
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jrtc27 wrote:

There's nothing FPR-y about the index itself though? It just happens to only be applicable for FPRs.

https://github.com/llvm/llvm-project/pull/77173