[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

[Eymen Ünay via llvm-commits]

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@@ -0,0 +1,58 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Skeleton data structures                                                   *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+using namespace llvm::jitlink::aarch32;
+
+namespace llvm {
+namespace jitlink {
+namespace aarch32 {
+template <> struct FixupInfo<Arm_MovwAbsNC> : public FixupInfoArm {
+  static constexpr uint32_t Opcode = 0x3000000;
+  static constexpr uint32_t OpcodeMask = 0xff00000;
+  static constexpr uint32_t ImmMask = 0xf0fff;
+  static constexpr uint32_t RegMask = 0xf000;
+};
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eymay wrote:

I agree, we may want to add more bits for unforeseeable new features. However, I think we can have a core set of encodings common to most instructions like Opcode and OpcodeMask. These don't have to be explicitly set as we do similarly for common opcodes already. I am to take out these commonalities into Base structs.

https://github.com/llvm/llvm-project/pull/76996