[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Leandro Lupori via llvm-commits]

luporl wrote:

Thanks for all the answers and improvements!

> > Are there any improvements with the unmodified version too?
> 
> The improvement without modification has not been confirmed because the analysis required for the pipeliner doesn't work well and MachinePipeliner cannot be applied. We recognize that this is an issue and would like to resolve.
> 
> > Finally, it would help if you could try this patch with other benchmarks, like SPEC CPU 2017, if it's not too much work, to check how it impacts the performance of other workloads.
> 
> For the same reason as above, we've not been able to check the performance with other benchmarks. Please let this be a future work.

So is the issue caused by some loops failing to match MachinePipeliner's expectations and then being skipped by it?
If this is the case I don't see any issue in letting this be a future work.

https://github.com/llvm/llvm-project/pull/74807