[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Carlos Eduardo Seo via llvm-commits]

ceseo wrote:

> IIUIC, by following the discourse thread and checking the results at [#65609 (comment)](https://github.com/llvm/llvm-project/pull/65609#issuecomment-1820943921), this patch reduces the number of cycles needed to execute the loop of https://github.com/AMReX-Codes/amrex/blob/9e35dc19489dc5d312e92781cb0471d282cf8370/Src/LinearSolvers/MLMG/AMReX_MLNodeLap_2D_K.H#L584, with some modifications. In this test code, with this patch applied, II would be changed from 11 to 20, to avoid spills/fills, which results in the number of cycles per iteration going down from 29.3 to 16.5, without MVE (#65609), and from 19.6 to 15.7 with MVE. Is that correct?
> 

Thanks, I missed that.

> It would be nice to add a short version of the results to the description of this patch, to give an idea of the performance improvement, without the need to go through discourse and the MVE patch.
> 
> Also, it would be nice if the modifications made to the test code could be made public, so that others can try to reproduce the results. Are there any improvements with the unmodified version too?
> 

I'd add a benchmark to the LLVM test-suite. It would make it easier to catch any future performance regressions.

https://github.com/llvm/llvm-project/pull/74807