[llvm] [RISCV] Add support predicating for ANDN/ORN/XNOR with short-forward-branch-opt. (PR #77077)

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git-clang-format --diff d933b88b71b00461815667d7cd0bb2fecd8606db 131f462064ba088e23cee62b05f191486681f973 -- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index e4be90afc4..f077972f12 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -228,9 +228,15 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
     case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
     case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
     case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
-    case RISCV::PseudoCCANDN:  NewOpc = RISCV::ANDN;  break;
-    case RISCV::PseudoCCORN:   NewOpc = RISCV::ORN;   break;
-    case RISCV::PseudoCCXNOR:  NewOpc = RISCV::XNOR;  break;
+    case RISCV::PseudoCCANDN:
+      NewOpc = RISCV::ANDN;
+      break;
+    case RISCV::PseudoCCORN:
+      NewOpc = RISCV::ORN;
+      break;
+    case RISCV::PseudoCCXNOR:
+      NewOpc = RISCV::XNOR;
+      break;
     }
     BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
         .add(MI.getOperand(5))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d25b6534e4..056d769858 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1350,9 +1350,15 @@ unsigned getPredicatedOpcode(const RISCVSubtarget &STI, unsigned Opcode) {
 
   if (STI.hasStdExtZbbOrZbkb()) {
     switch (Opcode) {
-    case RISCV::ANDN: return RISCV::PseudoCCANDN; break;
-    case RISCV::ORN:  return RISCV::PseudoCCORN;  break;
-    case RISCV::XNOR: return RISCV::PseudoCCXNOR; break;
+    case RISCV::ANDN:
+      return RISCV::PseudoCCANDN;
+      break;
+    case RISCV::ORN:
+      return RISCV::PseudoCCORN;
+      break;
+    case RISCV::XNOR:
+      return RISCV::PseudoCCXNOR;
+      break;
     }
   }
 

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https://github.com/llvm/llvm-project/pull/77077