[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Leandro Lupori via llvm-commits]

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@@ -1957,6 +2329,41 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
   });
 }
 
+/// Create a instruction stream that represents a single iteration and stage of
+/// each instruction. This function differs from SMSchedule::finalizeSchedule in
+/// that this doesn't have any side-effect to SwingSchedulerDAG. That is, this
+/// function is approximation of SMSchedule::finalizeSchedule with all non-const
+/// operations removed
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luporl wrote:

```suggestion
/// Create an instruction stream that represents a single iteration and stage of
/// each instruction. This function differs from SMSchedule::finalizeSchedule in
/// that this doesn't have any side-effect to SwingSchedulerDAG. That is, this
/// function is an approximation of SMSchedule::finalizeSchedule with all non-const
/// operations removed.
```

https://github.com/llvm/llvm-project/pull/74807