[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Carlos Eduardo Seo via llvm-commits]

ceseo wrote:

> In software pipelining, when searching for the Initiation Interval (II), `MachinePipeliner` tries to reduce register pressure, but doesn't check how many variables can actually alive at the same time. This can result a lot of register spills/fills can be generated after register allocation, which might cause performance degradation. 

Do you have any benchmark numbers showing this performance degradation and how this patch improves it?

https://github.com/llvm/llvm-project/pull/74807