[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 2 01:19:42 PST 2024
================
@@ -1231,16 +1231,17 @@ define <vscale x 1 x i64> @ctlz_nxv1i64(<vscale x 1 x i64> %va) {
;
; CHECK-F-LABEL: ctlz_nxv1i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-F-NEXT: vmv.v.x v9, a0
+; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-F-NEXT: vsrl.vi v8, v9, 23
-; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-F-NEXT: vzext.vf2 v9, v8
-; CHECK-F-NEXT: li a1, 190
-; CHECK-F-NEXT: vrsub.vx v8, v9, a1
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-F-NEXT: vsrl.vi v8, v10, 23
+; CHECK-F-NEXT: vwsubu.wv v9, v9, v8
; CHECK-F-NEXT: li a1, 64
-; CHECK-F-NEXT: vminu.vx v8, v8, a1
+; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
----------------
wangpc-pp wrote:
Yes, I agree! I meant something else, please see another comment. :-)
https://github.com/llvm/llvm-project/pull/72340
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