[llvm] [RISCV][GlobalISel] Zbkb support for G_ROTL and G_ROTR (PR #76599)

[Craig Topper via llvm-commits]

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@@ -101,7 +101,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
 
   auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
-  if (ST.hasStdExtZbb()) {
+  if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) {
     RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}});
     // Widen s32 rotate amount to s64 so SDAG patterns will match.
     if (ST.is64Bit())
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topperc wrote:

How would we ever get that input? The MIR from IRTranslator should have the same type for both operands since that's what's required by middle end IR for the fshl/fshr intrinsic.

https://github.com/llvm/llvm-project/pull/76599