[llvm] [RISCV][GlobalISel] Zbkb support for G_ROTL and G_ROTR (PR #76599)
Mikhail Gudim via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 29 19:34:49 PST 2023
================
@@ -101,7 +101,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
- if (ST.hasStdExtZbb()) {
+ if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) {
RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}});
// Widen s32 rotate amount to s64 so SDAG patterns will match.
if (ST.is64Bit())
----------------
mgudim wrote:
Is the next line correct?
```
RotateActions.widenScalarIf(all(typeIs(0, s32), typeIs(1, s32)),
changeTo(1, sXLen));
```
should we remove `typeIs(0, s32)`? The legalizer hangs on this input:
```
name: rotl_s64_s32
body: |
bb.1:
liveins: $x10, $x11
%2:_(s64) = COPY $x10
%3:_(s64) = COPY $x11
%1:_(s32) = G_TRUNC %3(s64)
%4:_(s64) = G_ROTL %2, %1(s32)
$x10 = COPY %4(s64)
PseudoRET implicit $x10
```
https://github.com/llvm/llvm-project/pull/76599
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