[llvm] [LoongArch] Emit function call code sequence as `PCADDU18I+JIRL` in medium code model (PR #76555)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 29 00:36:41 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc
Author: wanglei (wangleiat)
<details>
<summary>Changes</summary>
Adjustments made in accordance with psABI v2.30:
1. Moved the expansion of relevant pseudo-instructions from `LoongArchPreRAExpandPseudo` pass to `LoongArchExpandPseudo` pass, to ensure that the code sequences of `PseudoLA*_LARGE` instructions and Medium code model's function call are not scheduled.
2. AsmParser now supports parsing for call36 and tail36 macro instructions.
---
Patch is 63.37 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/76555.diff
20 Files Affected:
- (modified) llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp (+61)
- (modified) llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp (+264-258)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+22-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.h (+4)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.td (+97-9)
- (modified) llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp (+3)
- (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2-2)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h (+1)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp (+2)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h (+5-1)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp (+3)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp (+3)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h (+1)
- (modified) llvm/test/CodeGen/LoongArch/code-models.ll (+22-22)
- (modified) llvm/test/CodeGen/LoongArch/expand-call.ll (+1-1)
- (modified) llvm/test/CodeGen/LoongArch/global-address.ll (+20-16)
- (modified) llvm/test/CodeGen/LoongArch/tls-models.ll (+34-34)
- (modified) llvm/test/MC/LoongArch/Basic/Integer/invalid64.s (+1-1)
- (added) llvm/test/MC/LoongArch/Macros/macros-call.s (+10)
- (modified) llvm/test/MC/LoongArch/Relocations/relocations.s (+5)
``````````diff
diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index 66a37fce5dda11..46f63a4103f9f9 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -121,6 +121,10 @@ class LoongArchAsmParser : public MCTargetAsmParser {
// Helper to emit pseudo instruction "li.w/d $rd, $imm".
void emitLoadImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
+ // Helper to emit pseudo instruction "call36 sym" or "tail36 $rj, sym".
+ void emitFuncCall36(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ bool IsTailCall);
+
public:
enum LoongArchMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
@@ -400,6 +404,22 @@ class LoongArchOperand : public MCParsedAsmOperand {
IsValidKind;
}
+ bool isSImm20pcaddu18i() const {
+ if (!isImm())
+ return false;
+
+ int64_t Imm;
+ LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
+ VK == LoongArchMCExpr::VK_LoongArch_CALL36;
+
+ return IsConstantImm
+ ? isInt<20>(Imm) && IsValidKind
+ : LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
+ IsValidKind;
+ }
+
bool isSImm21lsl2() const {
if (!isImm())
return false;
@@ -1110,6 +1130,35 @@ void LoongArchAsmParser::emitLoadImm(MCInst &Inst, SMLoc IDLoc,
}
}
+void LoongArchAsmParser::emitFuncCall36(MCInst &Inst, SMLoc IDLoc,
+ MCStreamer &Out, bool IsTailCall) {
+ // call36 sym
+ // expands to:
+ // pcaddu18i $ra, %call36(sym)
+ // jirl $ra, $ra, 0
+ //
+ // tail36 $rj, sym
+ // expands to:
+ // pcaddu18i $rj, %call36(sym)
+ // jirl $r0, $rj, 0
+ unsigned ScratchReg =
+ IsTailCall ? Inst.getOperand(0).getReg() : (unsigned)LoongArch::R1;
+ const MCExpr *Sym =
+ IsTailCall ? Inst.getOperand(1).getExpr() : Inst.getOperand(0).getExpr();
+ const LoongArchMCExpr *LE = LoongArchMCExpr::create(
+ Sym, llvm::LoongArchMCExpr::VK_LoongArch_CALL36, getContext());
+
+ Out.emitInstruction(
+ MCInstBuilder(LoongArch::PCADDU18I).addReg(ScratchReg).addExpr(LE),
+ getSTI());
+ Out.emitInstruction(
+ MCInstBuilder(LoongArch::JIRL)
+ .addReg(IsTailCall ? (unsigned)LoongArch::R0 : ScratchReg)
+ .addReg(ScratchReg)
+ .addImm(0),
+ getSTI());
+}
+
bool LoongArchAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
OperandVector &Operands,
MCStreamer &Out) {
@@ -1158,6 +1207,12 @@ bool LoongArchAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case LoongArch::PseudoLI_D:
emitLoadImm(Inst, IDLoc, Out);
return false;
+ case LoongArch::PseudoCALL36:
+ emitFuncCall36(Inst, IDLoc, Out, /*IsTailCall=*/false);
+ return false;
+ case LoongArch::PseudoTAIL36:
+ emitFuncCall36(Inst, IDLoc, Out, /*IsTailCall=*/true);
+ return false;
}
Out.emitInstruction(Inst, getSTI());
return false;
@@ -1439,6 +1494,12 @@ bool LoongArchAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
/*Upper=*/(1 << 19) - 1,
"operand must be a symbol with modifier (e.g. %pc_hi20) or an integer "
"in the range");
+ case Match_InvalidSImm20pcaddu18i:
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, /*Lower=*/-(1 << 19),
+ /*Upper=*/(1 << 19) - 1,
+ "operand must be a symbol with modifier (e.g. %call36) or an integer "
+ "in the range");
case Match_InvalidSImm21lsl2:
return generateImmOutOfRangeError(
Operands, ErrorInfo, /*Lower=*/-(1 << 22), /*Upper=*/(1 << 22) - 4,
diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
index 72c1f1cec19834..f977f176066a5c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
@@ -62,43 +62,24 @@ class LoongArchPreRAExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator &NextMBBI,
unsigned FlagsHi, unsigned SecondOpcode,
unsigned FlagsLo);
- bool expandLargeAddressLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned LastOpcode, unsigned IdentifyingMO);
- bool expandLargeAddressLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned LastOpcode, unsigned IdentifyingMO,
- const MachineOperand &Symbol, Register DestReg,
- bool EraseFromParent);
bool expandLoadAddressPcrel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressGot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSLE(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSIE(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSLD(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSGD(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
- bool expandFunctionCALL(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool IsTailCall);
+ MachineBasicBlock::iterator &NextMBBI);
};
char LoongArchPreRAExpandPseudo::ID = 0;
@@ -131,30 +112,16 @@ bool LoongArchPreRAExpandPseudo::expandMI(
switch (MBBI->getOpcode()) {
case LoongArch::PseudoLA_PCREL:
return expandLoadAddressPcrel(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_PCREL_LARGE:
- return expandLoadAddressPcrel(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_GOT:
return expandLoadAddressGot(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_GOT_LARGE:
- return expandLoadAddressGot(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_LE:
return expandLoadAddressTLSLE(MBB, MBBI, NextMBBI);
case LoongArch::PseudoLA_TLS_IE:
return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_IE_LARGE:
- return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_LD:
return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_LD_LARGE:
- return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_GD:
return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_GD_LARGE:
- return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI, /*Large=*/true);
- case LoongArch::PseudoCALL:
- return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
- case LoongArch::PseudoTAIL:
- return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
}
return false;
}
@@ -187,118 +154,9 @@ bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
return true;
}
-bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
- unsigned IdentifyingMO) {
- MachineInstr &MI = *MBBI;
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LastOpcode, IdentifyingMO,
- MI.getOperand(2), MI.getOperand(0).getReg(),
- true);
-}
-
-bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
- unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
- bool EraseFromParent) {
- // Code Sequence:
- //
- // Part1: pcalau12i $scratch, %MO1(sym)
- // Part0: addi.d $dest, $zero, %MO0(sym)
- // Part2: lu32i.d $dest, %MO2(sym)
- // Part3: lu52i.d $dest, $dest, %MO3(sym)
- // Fin: LastOpcode $dest, $dest, $scratch
-
- unsigned MO0, MO1, MO2, MO3;
- switch (IdentifyingMO) {
- default:
- llvm_unreachable("unsupported identifying MO");
- case LoongArchII::MO_PCREL_LO:
- MO0 = IdentifyingMO;
- MO1 = LoongArchII::MO_PCREL_HI;
- MO2 = LoongArchII::MO_PCREL64_LO;
- MO3 = LoongArchII::MO_PCREL64_HI;
- break;
- case LoongArchII::MO_GOT_PC_HI:
- case LoongArchII::MO_LD_PC_HI:
- case LoongArchII::MO_GD_PC_HI:
- // These cases relocate just like the GOT case, except for Part1.
- MO0 = LoongArchII::MO_GOT_PC_LO;
- MO1 = IdentifyingMO;
- MO2 = LoongArchII::MO_GOT_PC64_LO;
- MO3 = LoongArchII::MO_GOT_PC64_HI;
- break;
- case LoongArchII::MO_IE_PC_LO:
- MO0 = IdentifyingMO;
- MO1 = LoongArchII::MO_IE_PC_HI;
- MO2 = LoongArchII::MO_IE_PC64_LO;
- MO3 = LoongArchII::MO_IE_PC64_HI;
- break;
- }
-
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
- assert(MF->getSubtarget<LoongArchSubtarget>().is64Bit() &&
- "Large code model requires LA64");
-
- Register TmpPart1 =
- MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
- Register TmpPart0 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
- Register TmpParts02 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
- Register TmpParts023 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
-
- auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), TmpPart1);
- auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), TmpPart0)
- .addReg(LoongArch::R0);
- auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), TmpParts02)
- // "rj" is needed due to InstrInfo pattern requirement.
- .addReg(TmpPart0, RegState::Kill);
- auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), TmpParts023)
- .addReg(TmpParts02, RegState::Kill);
- BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg)
- .addReg(TmpParts023)
- .addReg(TmpPart1, RegState::Kill);
-
- if (Symbol.getType() == MachineOperand::MO_ExternalSymbol) {
- const char *SymName = Symbol.getSymbolName();
- Part0.addExternalSymbol(SymName, MO0);
- Part1.addExternalSymbol(SymName, MO1);
- Part2.addExternalSymbol(SymName, MO2);
- Part3.addExternalSymbol(SymName, MO3);
- } else {
- Part0.addDisp(Symbol, 0, MO0);
- Part1.addDisp(Symbol, 0, MO1);
- Part2.addDisp(Symbol, 0, MO2);
- Part3.addDisp(Symbol, 0, MO3);
- }
-
- if (EraseFromParent)
- MI.eraseFromParent();
-
- return true;
-}
-
bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%pc` family of
- // relocs.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_PCREL_LO);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %pc_hi20(sym)
// addi.w/d $rd, $rd, %pc_lo12(sym)
@@ -311,13 +169,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, loading the result from GOT with `ldx.d` in the end.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
- LoongArchII::MO_GOT_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %got_pc_hi20(sym)
// ld.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -378,13 +230,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%ie_pc` family
- // of relocs, loading the result with `ldx.d` in the end.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
- LoongArchII::MO_IE_PC_LO);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %ie_pc_hi20(sym)
// ld.w/d $rd, $rd, %ie_pc_lo12(sym)
@@ -397,13 +243,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, with the `pcalau12i` insn relocated with `%ld_pc_hi20`.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_LD_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %ld_pc_hi20(sym)
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -416,13 +256,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, with the `pcalau12i` insn relocated with `%gd_pc_hi20`.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_GD_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %gd_pc_hi20(sym)
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -433,88 +267,6 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
SecondOpcode, LoongArchII::MO_GOT_PC_LO);
}
-bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
- const MachineOperand &Func = MI.getOperand(0);
- MachineInstrBuilder CALL;
- unsigned Opcode;
-
- switch (MF->getTarget().getCodeModel()) {
- default:
- report_fatal_error("Unsupported code model");
- break;
- case CodeModel::Small: {
- // CALL:
- // bl func
- // TAIL:
- // b func
- Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
- break;
- }
- case CodeModel::Medium: {
- // CALL:
- // pcalau12i $ra, %pc_hi20(func)
- // jirl $ra, $ra, %pc_lo12(func)
- // TAIL:
- // pcalau12i $scratch, %pc_hi20(func)
- // jirl $r0, $scratch, %pc_lo12(func)
- Opcode =
- IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
- Register ScratchReg =
- IsTailCall
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : LoongArch::R1;
- MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg);
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg);
- if (Func.isSymbol()) {
- const char *FnName = Func.getSymbolName();
- MIB.addExternalSymbol(FnName, LoongArchII::MO_PCREL_HI);
- CALL.addExternalSymbol(FnName, LoongArchII::MO_PCREL_LO);
- break;
- }
- assert(Func.isGlobal() && "Expected a GlobalValue at this time");
- const GlobalValue *GV = Func.getGlobal();
- MIB.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_HI);
- CALL.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_LO);
- break;
- }
- case CodeModel::Large: {
- // Emit the 5-insn large address load sequence, either directly or
- // indirectly in case of going through the GOT, then JIRL_TAIL or
- // JIRL_CALL to $addr.
- Opcode =
- IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
- Register AddrReg =
- IsTailCall
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : LoongArch::R1;
-
- bool UseGOT = Func.isGlobal() && !Func.getGlobal()->isDSOLocal();
- unsigned MO = UseGOT ? LoongArchII::MO_GOT_PC_HI : LoongArchII::MO_PCREL_LO;
- unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
- expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
- false);
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
- break;
- }
- }
-
- // Transfer implicit operands.
- CALL.copyImplicitOps(MI);
-
- // Transfer MI flags.
- CALL.setMIFlags(MI.getFlags());
-
- MI.eraseFromParent();
- return true;
-}
-
class LoongArchExpandPseudo : public MachineFunctionPass {
public:
const LoongArchInstrInfo *TII;
@@ -536,6 +288,35 @@ class LoongArchExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator &NextMBBI);
bool expandCopyCFR(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
+ bool expandLargeAddressLoad(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LastOpcode, unsigned IdentifyingMO);
+ bool expandLargeAddressLoad(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LastOpcode, unsigned IdentifyingMO,
+ const MachineOperand &Symbol, Register DestReg,
+ bool EraseFromParent);
+ bool expandLoadAddressPcrelLarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddressGotLarge(MachineBasicBlock &MBB,
+ MachineBasicBlo...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/76555
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