[llvm] [LoongArch] Emit function call code sequence as `PCADDU18I+JIRL` in medium code model (PR #76555)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 29 00:36:15 PST 2023
https://github.com/wangleiat created https://github.com/llvm/llvm-project/pull/76555
Adjustments made in accordance with psABI v2.30:
1. Moved the expansion of relevant pseudo-instructions from `LoongArchPreRAExpandPseudo` pass to `LoongArchExpandPseudo` pass, to ensure that the code sequences of `PseudoLA*_LARGE` instructions and Medium code model's function call are not scheduled.
2. AsmParser now supports parsing for call36 and tail36 macro instructions.
>From 518ca10009594de8315b345c925ac62cb17799f3 Mon Sep 17 00:00:00 2001
From: wanglei <wanglei at loongson.cn>
Date: Thu, 14 Dec 2023 15:27:17 +0800
Subject: [PATCH] [LoongArch] Emit function call code sequence as
`PCADDU18I+JIRL` in medium code model
Adjustments made in accordance with psABI v2.30:
1. Moved the expansion of relevant pseudo-instructions from
`LoongArchPreRAExpandPseudo` pass to `LoongArchExpandPseudo` pass,
to ensure that the code sequences of `PseudoLA*_LARGE` instructions
and Medium code model's function call are not scheduled.
2. AsmParser now supports parsing for call36 and tail36 macro
instructions.
---
.../AsmParser/LoongArchAsmParser.cpp | 61 ++
.../LoongArch/LoongArchExpandPseudoInsts.cpp | 522 +++++++++---------
.../LoongArch/LoongArchISelLowering.cpp | 24 +-
.../Target/LoongArch/LoongArchISelLowering.h | 4 +
.../Target/LoongArch/LoongArchInstrInfo.td | 106 +++-
.../Target/LoongArch/LoongArchMCInstLower.cpp | 3 +
.../LoongArch/LoongArchTargetMachine.cpp | 4 +-
.../MCTargetDesc/LoongArchBaseInfo.h | 1 +
.../MCTargetDesc/LoongArchELFObjectWriter.cpp | 2 +
.../MCTargetDesc/LoongArchFixupKinds.h | 6 +-
.../MCTargetDesc/LoongArchMCCodeEmitter.cpp | 3 +
.../MCTargetDesc/LoongArchMCExpr.cpp | 3 +
.../LoongArch/MCTargetDesc/LoongArchMCExpr.h | 1 +
llvm/test/CodeGen/LoongArch/code-models.ll | 44 +-
llvm/test/CodeGen/LoongArch/expand-call.ll | 2 +-
llvm/test/CodeGen/LoongArch/global-address.ll | 36 +-
llvm/test/CodeGen/LoongArch/tls-models.ll | 68 +--
.../MC/LoongArch/Basic/Integer/invalid64.s | 2 +-
llvm/test/MC/LoongArch/Macros/macros-call.s | 10 +
.../MC/LoongArch/Relocations/relocations.s | 5 +
20 files changed, 561 insertions(+), 346 deletions(-)
create mode 100644 llvm/test/MC/LoongArch/Macros/macros-call.s
diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index 66a37fce5dda11..46f63a4103f9f9 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -121,6 +121,10 @@ class LoongArchAsmParser : public MCTargetAsmParser {
// Helper to emit pseudo instruction "li.w/d $rd, $imm".
void emitLoadImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
+ // Helper to emit pseudo instruction "call36 sym" or "tail36 $rj, sym".
+ void emitFuncCall36(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ bool IsTailCall);
+
public:
enum LoongArchMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
@@ -400,6 +404,22 @@ class LoongArchOperand : public MCParsedAsmOperand {
IsValidKind;
}
+ bool isSImm20pcaddu18i() const {
+ if (!isImm())
+ return false;
+
+ int64_t Imm;
+ LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
+ VK == LoongArchMCExpr::VK_LoongArch_CALL36;
+
+ return IsConstantImm
+ ? isInt<20>(Imm) && IsValidKind
+ : LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
+ IsValidKind;
+ }
+
bool isSImm21lsl2() const {
if (!isImm())
return false;
@@ -1110,6 +1130,35 @@ void LoongArchAsmParser::emitLoadImm(MCInst &Inst, SMLoc IDLoc,
}
}
+void LoongArchAsmParser::emitFuncCall36(MCInst &Inst, SMLoc IDLoc,
+ MCStreamer &Out, bool IsTailCall) {
+ // call36 sym
+ // expands to:
+ // pcaddu18i $ra, %call36(sym)
+ // jirl $ra, $ra, 0
+ //
+ // tail36 $rj, sym
+ // expands to:
+ // pcaddu18i $rj, %call36(sym)
+ // jirl $r0, $rj, 0
+ unsigned ScratchReg =
+ IsTailCall ? Inst.getOperand(0).getReg() : (unsigned)LoongArch::R1;
+ const MCExpr *Sym =
+ IsTailCall ? Inst.getOperand(1).getExpr() : Inst.getOperand(0).getExpr();
+ const LoongArchMCExpr *LE = LoongArchMCExpr::create(
+ Sym, llvm::LoongArchMCExpr::VK_LoongArch_CALL36, getContext());
+
+ Out.emitInstruction(
+ MCInstBuilder(LoongArch::PCADDU18I).addReg(ScratchReg).addExpr(LE),
+ getSTI());
+ Out.emitInstruction(
+ MCInstBuilder(LoongArch::JIRL)
+ .addReg(IsTailCall ? (unsigned)LoongArch::R0 : ScratchReg)
+ .addReg(ScratchReg)
+ .addImm(0),
+ getSTI());
+}
+
bool LoongArchAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
OperandVector &Operands,
MCStreamer &Out) {
@@ -1158,6 +1207,12 @@ bool LoongArchAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case LoongArch::PseudoLI_D:
emitLoadImm(Inst, IDLoc, Out);
return false;
+ case LoongArch::PseudoCALL36:
+ emitFuncCall36(Inst, IDLoc, Out, /*IsTailCall=*/false);
+ return false;
+ case LoongArch::PseudoTAIL36:
+ emitFuncCall36(Inst, IDLoc, Out, /*IsTailCall=*/true);
+ return false;
}
Out.emitInstruction(Inst, getSTI());
return false;
@@ -1439,6 +1494,12 @@ bool LoongArchAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
/*Upper=*/(1 << 19) - 1,
"operand must be a symbol with modifier (e.g. %pc_hi20) or an integer "
"in the range");
+ case Match_InvalidSImm20pcaddu18i:
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, /*Lower=*/-(1 << 19),
+ /*Upper=*/(1 << 19) - 1,
+ "operand must be a symbol with modifier (e.g. %call36) or an integer "
+ "in the range");
case Match_InvalidSImm21lsl2:
return generateImmOutOfRangeError(
Operands, ErrorInfo, /*Lower=*/-(1 << 22), /*Upper=*/(1 << 22) - 4,
diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
index 72c1f1cec19834..f977f176066a5c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
@@ -62,43 +62,24 @@ class LoongArchPreRAExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator &NextMBBI,
unsigned FlagsHi, unsigned SecondOpcode,
unsigned FlagsLo);
- bool expandLargeAddressLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned LastOpcode, unsigned IdentifyingMO);
- bool expandLargeAddressLoad(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned LastOpcode, unsigned IdentifyingMO,
- const MachineOperand &Symbol, Register DestReg,
- bool EraseFromParent);
bool expandLoadAddressPcrel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressGot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSLE(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSIE(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSLD(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
+ MachineBasicBlock::iterator &NextMBBI);
bool expandLoadAddressTLSGD(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool Large = false);
- bool expandFunctionCALL(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- bool IsTailCall);
+ MachineBasicBlock::iterator &NextMBBI);
};
char LoongArchPreRAExpandPseudo::ID = 0;
@@ -131,30 +112,16 @@ bool LoongArchPreRAExpandPseudo::expandMI(
switch (MBBI->getOpcode()) {
case LoongArch::PseudoLA_PCREL:
return expandLoadAddressPcrel(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_PCREL_LARGE:
- return expandLoadAddressPcrel(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_GOT:
return expandLoadAddressGot(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_GOT_LARGE:
- return expandLoadAddressGot(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_LE:
return expandLoadAddressTLSLE(MBB, MBBI, NextMBBI);
case LoongArch::PseudoLA_TLS_IE:
return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_IE_LARGE:
- return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_LD:
return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_LD_LARGE:
- return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI, /*Large=*/true);
case LoongArch::PseudoLA_TLS_GD:
return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI);
- case LoongArch::PseudoLA_TLS_GD_LARGE:
- return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI, /*Large=*/true);
- case LoongArch::PseudoCALL:
- return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
- case LoongArch::PseudoTAIL:
- return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
}
return false;
}
@@ -187,118 +154,9 @@ bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
return true;
}
-bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
- unsigned IdentifyingMO) {
- MachineInstr &MI = *MBBI;
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LastOpcode, IdentifyingMO,
- MI.getOperand(2), MI.getOperand(0).getReg(),
- true);
-}
-
-bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
- unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
- bool EraseFromParent) {
- // Code Sequence:
- //
- // Part1: pcalau12i $scratch, %MO1(sym)
- // Part0: addi.d $dest, $zero, %MO0(sym)
- // Part2: lu32i.d $dest, %MO2(sym)
- // Part3: lu52i.d $dest, $dest, %MO3(sym)
- // Fin: LastOpcode $dest, $dest, $scratch
-
- unsigned MO0, MO1, MO2, MO3;
- switch (IdentifyingMO) {
- default:
- llvm_unreachable("unsupported identifying MO");
- case LoongArchII::MO_PCREL_LO:
- MO0 = IdentifyingMO;
- MO1 = LoongArchII::MO_PCREL_HI;
- MO2 = LoongArchII::MO_PCREL64_LO;
- MO3 = LoongArchII::MO_PCREL64_HI;
- break;
- case LoongArchII::MO_GOT_PC_HI:
- case LoongArchII::MO_LD_PC_HI:
- case LoongArchII::MO_GD_PC_HI:
- // These cases relocate just like the GOT case, except for Part1.
- MO0 = LoongArchII::MO_GOT_PC_LO;
- MO1 = IdentifyingMO;
- MO2 = LoongArchII::MO_GOT_PC64_LO;
- MO3 = LoongArchII::MO_GOT_PC64_HI;
- break;
- case LoongArchII::MO_IE_PC_LO:
- MO0 = IdentifyingMO;
- MO1 = LoongArchII::MO_IE_PC_HI;
- MO2 = LoongArchII::MO_IE_PC64_LO;
- MO3 = LoongArchII::MO_IE_PC64_HI;
- break;
- }
-
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
- assert(MF->getSubtarget<LoongArchSubtarget>().is64Bit() &&
- "Large code model requires LA64");
-
- Register TmpPart1 =
- MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
- Register TmpPart0 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
- Register TmpParts02 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
- Register TmpParts023 =
- DestReg.isVirtual()
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : DestReg;
-
- auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), TmpPart1);
- auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), TmpPart0)
- .addReg(LoongArch::R0);
- auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), TmpParts02)
- // "rj" is needed due to InstrInfo pattern requirement.
- .addReg(TmpPart0, RegState::Kill);
- auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), TmpParts023)
- .addReg(TmpParts02, RegState::Kill);
- BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg)
- .addReg(TmpParts023)
- .addReg(TmpPart1, RegState::Kill);
-
- if (Symbol.getType() == MachineOperand::MO_ExternalSymbol) {
- const char *SymName = Symbol.getSymbolName();
- Part0.addExternalSymbol(SymName, MO0);
- Part1.addExternalSymbol(SymName, MO1);
- Part2.addExternalSymbol(SymName, MO2);
- Part3.addExternalSymbol(SymName, MO3);
- } else {
- Part0.addDisp(Symbol, 0, MO0);
- Part1.addDisp(Symbol, 0, MO1);
- Part2.addDisp(Symbol, 0, MO2);
- Part3.addDisp(Symbol, 0, MO3);
- }
-
- if (EraseFromParent)
- MI.eraseFromParent();
-
- return true;
-}
-
bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%pc` family of
- // relocs.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_PCREL_LO);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %pc_hi20(sym)
// addi.w/d $rd, $rd, %pc_lo12(sym)
@@ -311,13 +169,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, loading the result from GOT with `ldx.d` in the end.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
- LoongArchII::MO_GOT_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %got_pc_hi20(sym)
// ld.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -378,13 +230,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%ie_pc` family
- // of relocs, loading the result with `ldx.d` in the end.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
- LoongArchII::MO_IE_PC_LO);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %ie_pc_hi20(sym)
// ld.w/d $rd, $rd, %ie_pc_lo12(sym)
@@ -397,13 +243,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, with the `pcalau12i` insn relocated with `%ld_pc_hi20`.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_LD_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %ld_pc_hi20(sym)
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -416,13 +256,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool Large) {
- if (Large)
- // Emit the 5-insn large address load sequence with the `%got_pc` family
- // of relocs, with the `pcalau12i` insn relocated with `%gd_pc_hi20`.
- return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
- LoongArchII::MO_GD_PC_HI);
-
+ MachineBasicBlock::iterator &NextMBBI) {
// Code Sequence:
// pcalau12i $rd, %gd_pc_hi20(sym)
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
@@ -433,88 +267,6 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
SecondOpcode, LoongArchII::MO_GOT_PC_LO);
}
-bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
- const MachineOperand &Func = MI.getOperand(0);
- MachineInstrBuilder CALL;
- unsigned Opcode;
-
- switch (MF->getTarget().getCodeModel()) {
- default:
- report_fatal_error("Unsupported code model");
- break;
- case CodeModel::Small: {
- // CALL:
- // bl func
- // TAIL:
- // b func
- Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
- break;
- }
- case CodeModel::Medium: {
- // CALL:
- // pcalau12i $ra, %pc_hi20(func)
- // jirl $ra, $ra, %pc_lo12(func)
- // TAIL:
- // pcalau12i $scratch, %pc_hi20(func)
- // jirl $r0, $scratch, %pc_lo12(func)
- Opcode =
- IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
- Register ScratchReg =
- IsTailCall
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : LoongArch::R1;
- MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg);
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg);
- if (Func.isSymbol()) {
- const char *FnName = Func.getSymbolName();
- MIB.addExternalSymbol(FnName, LoongArchII::MO_PCREL_HI);
- CALL.addExternalSymbol(FnName, LoongArchII::MO_PCREL_LO);
- break;
- }
- assert(Func.isGlobal() && "Expected a GlobalValue at this time");
- const GlobalValue *GV = Func.getGlobal();
- MIB.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_HI);
- CALL.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_LO);
- break;
- }
- case CodeModel::Large: {
- // Emit the 5-insn large address load sequence, either directly or
- // indirectly in case of going through the GOT, then JIRL_TAIL or
- // JIRL_CALL to $addr.
- Opcode =
- IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
- Register AddrReg =
- IsTailCall
- ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
- : LoongArch::R1;
-
- bool UseGOT = Func.isGlobal() && !Func.getGlobal()->isDSOLocal();
- unsigned MO = UseGOT ? LoongArchII::MO_GOT_PC_HI : LoongArchII::MO_PCREL_LO;
- unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
- expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
- false);
- CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
- break;
- }
- }
-
- // Transfer implicit operands.
- CALL.copyImplicitOps(MI);
-
- // Transfer MI flags.
- CALL.setMIFlags(MI.getFlags());
-
- MI.eraseFromParent();
- return true;
-}
-
class LoongArchExpandPseudo : public MachineFunctionPass {
public:
const LoongArchInstrInfo *TII;
@@ -536,6 +288,35 @@ class LoongArchExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator &NextMBBI);
bool expandCopyCFR(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
+ bool expandLargeAddressLoad(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LastOpcode, unsigned IdentifyingMO);
+ bool expandLargeAddressLoad(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LastOpcode, unsigned IdentifyingMO,
+ const MachineOperand &Symbol, Register DestReg,
+ bool EraseFromParent);
+ bool expandLoadAddressPcrelLarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddressGotLarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddressTLSIELarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddressTLSLDLarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddressTLSGDLarge(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandFunctionCALL(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ bool IsTailCall);
};
char LoongArchExpandPseudo::ID = 0;
@@ -570,6 +351,24 @@ bool LoongArchExpandPseudo::expandMI(MachineBasicBlock &MBB,
switch (MBBI->getOpcode()) {
case LoongArch::PseudoCopyCFR:
return expandCopyCFR(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoLA_PCREL_LARGE:
+ return expandLoadAddressPcrelLarge(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoLA_GOT_LARGE:
+ return expandLoadAddressGotLarge(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoLA_TLS_IE_LARGE:
+ return expandLoadAddressTLSIELarge(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoLA_TLS_LD_LARGE:
+ return expandLoadAddressTLSLDLarge(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoLA_TLS_GD_LARGE:
+ return expandLoadAddressTLSGDLarge(MBB, MBBI, NextMBBI);
+ case LoongArch::PseudoCALL:
+ case LoongArch::PseudoCALL_MEDIUM:
+ case LoongArch::PseudoCALL_LARGE:
+ return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
+ case LoongArch::PseudoTAIL:
+ case LoongArch::PseudoTAIL_MEDIUM:
+ case LoongArch::PseudoTAIL_LARGE:
+ return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
}
return false;
@@ -628,6 +427,213 @@ bool LoongArchExpandPseudo::expandCopyCFR(
return true;
}
+bool LoongArchExpandPseudo::expandLargeAddressLoad(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
+ unsigned IdentifyingMO) {
+ MachineInstr &MI = *MBBI;
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LastOpcode, IdentifyingMO,
+ MI.getOperand(2), MI.getOperand(0).getReg(),
+ true);
+}
+
+bool LoongArchExpandPseudo::expandLargeAddressLoad(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
+ unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
+ bool EraseFromParent) {
+ // Code Sequence:
+ //
+ // Part1: pcalau12i $dst, %MO1(sym)
+ // Part0: addi.d $t8, $zero, %MO0(sym)
+ // Part2: lu32i.d $t8, %MO2(sym)
+ // Part3: lu52i.d $t8, $t8, %MO3(sym)
+ // Fin: LastOpcode $dst, $t8, $dst
+
+ unsigned MO0, MO1, MO2, MO3;
+ switch (IdentifyingMO) {
+ default:
+ llvm_unreachable("unsupported identifying MO");
+ case LoongArchII::MO_PCREL_LO:
+ MO0 = IdentifyingMO;
+ MO1 = LoongArchII::MO_PCREL_HI;
+ MO2 = LoongArchII::MO_PCREL64_LO;
+ MO3 = LoongArchII::MO_PCREL64_HI;
+ break;
+ case LoongArchII::MO_GOT_PC_HI:
+ case LoongArchII::MO_LD_PC_HI:
+ case LoongArchII::MO_GD_PC_HI:
+ // These cases relocate just like the GOT case, except for Part1.
+ MO0 = LoongArchII::MO_GOT_PC_LO;
+ MO1 = IdentifyingMO;
+ MO2 = LoongArchII::MO_GOT_PC64_LO;
+ MO3 = LoongArchII::MO_GOT_PC64_HI;
+ break;
+ case LoongArchII::MO_IE_PC_LO:
+ MO0 = IdentifyingMO;
+ MO1 = LoongArchII::MO_IE_PC_HI;
+ MO2 = LoongArchII::MO_IE_PC64_LO;
+ MO3 = LoongArchII::MO_IE_PC64_HI;
+ break;
+ }
+
+ MachineFunction *MF = MBB.getParent();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+ Register ScratchReg = LoongArch::R20; // $t8
+
+ assert(MF->getSubtarget<LoongArchSubtarget>().is64Bit() &&
+ "Large code model requires LA64");
+
+ auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), DestReg);
+ auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), ScratchReg)
+ .addReg(LoongArch::R0);
+ auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), ScratchReg)
+ // "rj" is needed due to InstrInfo pattern requirement.
+ .addReg(ScratchReg);
+ auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), ScratchReg)
+ .addReg(ScratchReg);
+ BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg)
+ .addReg(ScratchReg)
+ .addReg(DestReg);
+
+ if (Symbol.getType() == MachineOperand::MO_ExternalSymbol) {
+ const char *SymName = Symbol.getSymbolName();
+ Part0.addExternalSymbol(SymName, MO0);
+ Part1.addExternalSymbol(SymName, MO1);
+ Part2.addExternalSymbol(SymName, MO2);
+ Part3.addExternalSymbol(SymName, MO3);
+ } else {
+ Part0.addDisp(Symbol, 0, MO0);
+ Part1.addDisp(Symbol, 0, MO1);
+ Part2.addDisp(Symbol, 0, MO2);
+ Part3.addDisp(Symbol, 0, MO3);
+ }
+
+ if (EraseFromParent)
+ MI.eraseFromParent();
+
+ return true;
+}
+
+bool LoongArchExpandPseudo::expandLoadAddressPcrelLarge(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ // Emit the 5-insn large address load sequence with the `%pc` family of
+ // relocs.
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
+ LoongArchII::MO_PCREL_LO);
+}
+
+bool LoongArchExpandPseudo::expandLoadAddressGotLarge(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ // Emit the 5-insn large address load sequence with the `%got_pc` family
+ // of relocs, loading the result from GOT with `ldx.d` in the end.
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
+ LoongArchII::MO_GOT_PC_HI);
+}
+
+bool LoongArchExpandPseudo::expandLoadAddressTLSIELarge(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ // Emit the 5-insn large address load sequence with the `%ie_pc` family
+ // of relocs, loading the result with `ldx.d` in the end.
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
+ LoongArchII::MO_IE_PC_LO);
+}
+
+bool LoongArchExpandPseudo::expandLoadAddressTLSLDLarge(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ // Emit the 5-insn large address load sequence with the `%got_pc` family
+ // of relocs, with the `pcalau12i` insn relocated with `%ld_pc_hi20`.
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
+ LoongArchII::MO_LD_PC_HI);
+}
+
+bool LoongArchExpandPseudo::expandLoadAddressTLSGDLarge(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ // Emit the 5-insn large address load sequence with the `%got_pc` family
+ // of relocs, with the `pcalau12i` insn relocated with `%gd_pc_hi20`.
+ return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
+ LoongArchII::MO_GD_PC_HI);
+}
+
+bool LoongArchExpandPseudo::expandFunctionCALL(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
+ MachineFunction *MF = MBB.getParent();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+ const MachineOperand &Func = MI.getOperand(0);
+ MachineInstrBuilder CALL;
+ unsigned Opcode;
+
+ switch (MF->getTarget().getCodeModel()) {
+ default:
+ report_fatal_error("Unsupported code model");
+ break;
+ case CodeModel::Small: {
+ // CALL:
+ // bl func
+ // TAIL:
+ // b func
+ Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
+ CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
+ break;
+ }
+ case CodeModel::Medium: {
+ // CALL:
+ // pcaddu18i $ra, %call36(func)
+ // jirl $ra, $ra, 0
+ // TAIL:
+ // pcaddu18i $t8, %call36(func)
+ // jr $t8
+ Opcode =
+ IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
+ Register ScratchReg = IsTailCall ? LoongArch::R20 : LoongArch::R1;
+ MachineInstrBuilder MIB =
+ BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCADDU18I), ScratchReg);
+
+ CALL =
+ BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg).addImm(0);
+
+ if (Func.isSymbol())
+ MIB.addExternalSymbol(Func.getSymbolName(), LoongArchII::MO_CALL36);
+ else
+ MIB.addDisp(Func, 0, LoongArchII::MO_CALL36);
+ break;
+ }
+ case CodeModel::Large: {
+ // Emit the 5-insn large address load sequence, either directly or
+ // indirectly in case of going through the GOT, then JIRL_TAIL or
+ // JIRL_CALL to $addr.
+ Opcode =
+ IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
+ Register AddrReg = IsTailCall ? LoongArch::R19 : LoongArch::R1;
+
+ bool UseGOT = Func.isGlobal() && !Func.getGlobal()->isDSOLocal();
+ unsigned MO = UseGOT ? LoongArchII::MO_GOT_PC_HI : LoongArchII::MO_PCREL_LO;
+ unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
+ expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
+ false);
+ CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
+ break;
+ }
+ }
+
+ // Transfer implicit operands.
+ CALL.copyImplicitOps(MI);
+
+ // Transfer MI flags.
+ CALL.setMIFlags(MI.getFlags());
+
+ MI.eraseFromParent();
+ return true;
+}
+
} // end namespace
INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "loongarch-prera-expand-pseudo",
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 80853ee3198771..60709d03606946 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -3381,8 +3381,12 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
// TODO: Add more target-dependent nodes later.
NODE_NAME_CASE(CALL)
+ NODE_NAME_CASE(CALL_MEDIUM)
+ NODE_NAME_CASE(CALL_LARGE)
NODE_NAME_CASE(RET)
NODE_NAME_CASE(TAIL)
+ NODE_NAME_CASE(TAIL_MEDIUM)
+ NODE_NAME_CASE(TAIL_LARGE)
NODE_NAME_CASE(SLL_W)
NODE_NAME_CASE(SRA_W)
NODE_NAME_CASE(SRL_W)
@@ -4240,15 +4244,31 @@ LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
+ unsigned Op;
+ switch (DAG.getTarget().getCodeModel()) {
+ default:
+ report_fatal_error("Unsupported code model");
+ case CodeModel::Small:
+ Op = IsTailCall ? LoongArchISD::TAIL : LoongArchISD::CALL;
+ break;
+ case CodeModel::Medium:
+ assert(Subtarget.is64Bit() && "Medium code model requires LA64");
+ Op = IsTailCall ? LoongArchISD::TAIL_MEDIUM : LoongArchISD::CALL_MEDIUM;
+ break;
+ case CodeModel::Large:
+ assert(Subtarget.is64Bit() && "Large code model requires LA64");
+ Op = IsTailCall ? LoongArchISD::TAIL_LARGE : LoongArchISD::CALL_LARGE;
+ break;
+ }
if (IsTailCall) {
MF.getFrameInfo().setHasTailCall();
- SDValue Ret = DAG.getNode(LoongArchISD::TAIL, DL, NodeTys, Ops);
+ SDValue Ret = DAG.getNode(Op, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
return Ret;
}
- Chain = DAG.getNode(LoongArchISD::CALL, DL, NodeTys, Ops);
+ Chain = DAG.getNode(Op, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
Glue = Chain.getValue(1);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 6f8878f9ccd519..2875aa82e424de 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -27,8 +27,12 @@ enum NodeType : unsigned {
// TODO: add more LoongArchISDs
CALL,
+ CALL_MEDIUM,
+ CALL_LARGE,
RET,
TAIL,
+ TAIL_MEDIUM,
+ TAIL_LARGE,
// 32-bit shifts, directly matching the semantics of the named LoongArch
// instructions.
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 2fea0f33e9eb46..78074c0128766d 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -69,6 +69,18 @@ def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone,
def loongarch_tail : SDNode<"LoongArchISD::TAIL", SDT_LoongArchCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>;
+def loongarch_call_medium : SDNode<"LoongArchISD::CALL_MEDIUM", SDT_LoongArchCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
+def loongarch_tail_medium : SDNode<"LoongArchISD::TAIL_MEDIUM", SDT_LoongArchCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
+def loongarch_call_large : SDNode<"LoongArchISD::CALL_LARGE", SDT_LoongArchCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
+def loongarch_tail_large : SDNode<"LoongArchISD::TAIL_LARGE", SDT_LoongArchCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
@@ -377,6 +389,10 @@ def simm20_lu32id : SImm20Operand {
let ParserMatchClass = SImmAsmOperand<20, "lu32id">;
}
+def simm20_pcaddu18i : SImm20Operand {
+ let ParserMatchClass = SImmAsmOperand<20, "pcaddu18i">;
+}
+
def simm21_lsl2 : Operand<OtherVT> {
let ParserMatchClass = SImmAsmOperand<21, "lsl2">;
let EncoderMethod = "getImmOpValueAsr<2>";
@@ -832,7 +848,7 @@ def LU32I_D : Fmt1RI20<0x16000000, (outs GPR:$dst),
"$rd, $imm20">;
}
def LU52I_D : ALU_2RI12<0x03000000, simm12_lu52id>;
-def PCADDU18I : ALU_1RI20<0x1e000000, simm20>;
+def PCADDU18I : ALU_1RI20<0x1e000000, simm20_pcaddu18i>;
def MUL_D : ALU_3R<0x001d8000>;
def MULH_D : ALU_3R<0x001e0000>;
def MULH_DU : ALU_3R<0x001e8000>;
@@ -1395,16 +1411,43 @@ def : Pat<(brind GPR:$rj), (PseudoBRIND GPR:$rj, 0)>;
def : Pat<(brind (add GPR:$rj, simm16_lsl2:$imm16)),
(PseudoBRIND GPR:$rj, simm16_lsl2:$imm16)>;
+// Function call with 'Small' code model.
let isCall = 1, Defs = [R1] in
-def PseudoCALL : Pseudo<(outs), (ins simm26_symbol:$func)>;
+def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func)>;
def : Pat<(loongarch_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
def : Pat<(loongarch_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
+// Function call with 'Medium' code model.
+let isCall = 1, Defs = [R1, R20], Size = 8 in
+def PseudoCALL_MEDIUM : Pseudo<(outs), (ins bare_symbol:$func)>;
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_call_medium tglobaladdr:$func),
+ (PseudoCALL_MEDIUM tglobaladdr:$func)>;
+def : Pat<(loongarch_call_medium texternalsym:$func),
+ (PseudoCALL_MEDIUM texternalsym:$func)>;
+} // Predicates = [IsLA64]
+
+// Function call with 'Large' code model.
+let isCall = 1, Defs = [R1, R20], Size = 24 in
+def PseudoCALL_LARGE: Pseudo<(outs), (ins bare_symbol:$func)>;
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_call_large tglobaladdr:$func),
+ (PseudoCALL_LARGE tglobaladdr:$func)>;
+def : Pat<(loongarch_call_large texternalsym:$func),
+ (PseudoCALL_LARGE texternalsym:$func)>;
+} // Predicates = [IsLA64]
+
let isCall = 1, Defs = [R1] in
def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj),
[(loongarch_call GPR:$rj)]>,
PseudoInstExpansion<(JIRL R1, GPR:$rj, 0)>;
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_call_medium GPR:$rj), (PseudoCALLIndirect GPR:$rj)>;
+def : Pat<(loongarch_call_large GPR:$rj), (PseudoCALLIndirect GPR:$rj)>;
+}
let isCall = 1, hasSideEffects = 0, mayStore = 0, mayLoad = 0, Defs = [R1] in
def PseudoJIRL_CALL : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16)>,
@@ -1415,18 +1458,47 @@ let isBarrier = 1, isReturn = 1, isTerminator = 1 in
def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
PseudoInstExpansion<(JIRL R0, R1, 0)>;
+// Tail call with 'Small' code model.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
-def PseudoTAIL : Pseudo<(outs), (ins simm26_symbol:$dst)>;
+def PseudoTAIL : Pseudo<(outs), (ins bare_symbol:$dst)>;
def : Pat<(loongarch_tail (iPTR tglobaladdr:$dst)),
(PseudoTAIL tglobaladdr:$dst)>;
def : Pat<(loongarch_tail (iPTR texternalsym:$dst)),
(PseudoTAIL texternalsym:$dst)>;
+// Tail call with 'Medium' code model.
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+ Uses = [R3], Defs = [R20], Size = 8 in
+def PseudoTAIL_MEDIUM : Pseudo<(outs), (ins bare_symbol:$dst)>;
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_tail_medium (iPTR tglobaladdr:$dst)),
+ (PseudoTAIL_MEDIUM tglobaladdr:$dst)>;
+def : Pat<(loongarch_tail_medium (iPTR texternalsym:$dst)),
+ (PseudoTAIL_MEDIUM texternalsym:$dst)>;
+} // Predicates = [IsLA64]
+
+// Tail call with 'Large' code model.
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+ Uses = [R3], Defs = [R19, R20], Size = 24 in
+def PseudoTAIL_LARGE : Pseudo<(outs), (ins bare_symbol:$dst)>;
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_tail_large (iPTR tglobaladdr:$dst)),
+ (PseudoTAIL_LARGE tglobaladdr:$dst)>;
+def : Pat<(loongarch_tail_large (iPTR texternalsym:$dst)),
+ (PseudoTAIL_LARGE texternalsym:$dst)>;
+} // Predicates = [IsLA64]
+
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
def PseudoTAILIndirect : Pseudo<(outs), (ins GPRT:$rj),
[(loongarch_tail GPRT:$rj)]>,
PseudoInstExpansion<(JIRL R0, GPR:$rj, 0)>;
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_tail_medium GPR:$rj), (PseudoTAILIndirect GPR:$rj)>;
+def : Pat<(loongarch_tail_large GPR:$rj), (PseudoTAILIndirect GPR:$rj)>;
+}
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
hasSideEffects = 0, mayStore = 0, mayLoad = 0, Uses = [R3] in
@@ -1439,6 +1511,19 @@ def PseudoJIRL_TAIL : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16)>,
PseudoInstExpansion<(JIRL R0, GPR:$rj,
simm16_lsl2:$imm16)>;
+/// call36/taill36 macro instructions
+let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, isAsmParserOnly = 1,
+ Defs = [R1], Size = 8, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in
+def PseudoCALL36 : Pseudo<(outs), (ins bare_symbol:$dst), [],
+ "call36", "$dst">,
+ Requires<[IsLA64]>;
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3],
+ isCodeGenOnly = 0, isAsmParserOnly = 1, Size = 8, hasSideEffects = 0,
+ mayStore = 0, mayLoad = 0 in
+def PseudoTAIL36 : Pseudo<(outs), (ins GPR:$tmp, bare_symbol:$dst), [],
+ "tail36", "$tmp, $dst">,
+ Requires<[IsLA64]>;
+
/// Load address (la*) macro instructions.
// Define isCodeGenOnly = 0 to expose them to tablegened assembly parser.
@@ -1451,6 +1536,7 @@ def PseudoLA_ABS_LARGE : Pseudo<(outs GPR:$dst),
"la.abs", "$dst, $src">;
def PseudoLA_PCREL : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
"la.pcrel", "$dst, $src">;
+let Defs = [R20], Size = 20 in
def PseudoLA_PCREL_LARGE : Pseudo<(outs GPR:$dst),
(ins GPR:$tmp, bare_symbol:$src), [],
"la.pcrel", "$dst, $tmp, $src">,
@@ -1462,28 +1548,30 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
isAsmParserOnly = 1 in {
def PseudoLA_GOT : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
"la.got", "$dst, $src">;
+def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+ "la.tls.ie", "$dst, $src">;
+def PseudoLA_TLS_LD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+ "la.tls.ld", "$dst, $src">;
+def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+ "la.tls.gd", "$dst, $src">;
+let Defs = [R20], Size = 20 in {
def PseudoLA_GOT_LARGE : Pseudo<(outs GPR:$dst),
(ins GPR:$tmp, bare_symbol:$src), [],
"la.got", "$dst, $tmp, $src">,
Requires<[IsLA64]>;
-def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
- "la.tls.ie", "$dst, $src">;
def PseudoLA_TLS_IE_LARGE : Pseudo<(outs GPR:$dst),
(ins GPR:$tmp, bare_symbol:$src), [],
"la.tls.ie", "$dst, $tmp, $src">,
Requires<[IsLA64]>;
-def PseudoLA_TLS_LD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
- "la.tls.ld", "$dst, $src">;
def PseudoLA_TLS_LD_LARGE : Pseudo<(outs GPR:$dst),
(ins GPR:$tmp, bare_symbol:$src), [],
"la.tls.ld", "$dst, $tmp, $src">,
Requires<[IsLA64]>;
-def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
- "la.tls.gd", "$dst, $src">;
def PseudoLA_TLS_GD_LARGE : Pseudo<(outs GPR:$dst),
(ins GPR:$tmp, bare_symbol:$src), [],
"la.tls.gd", "$dst, $tmp, $src">,
Requires<[IsLA64]>;
+} // Defs = [R20], Size = 20
}
// Load address inst alias: "la", "la.global" and "la.local".
diff --git a/llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp b/llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
index 5daa9481c9072e..98ad49f25e3f2f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
@@ -95,6 +95,9 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
case LoongArchII::MO_GD_PC_HI:
Kind = LoongArchMCExpr::VK_LoongArch_TLS_GD_PC_HI20;
break;
+ case LoongArchII::MO_CALL36:
+ Kind = LoongArchMCExpr::VK_LoongArch_CALL36;
+ break;
// TODO: Handle more target-flags.
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index a5a4d78aceeef0..62ae1dea00d6f8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -63,11 +63,11 @@ getEffectiveLoongArchCodeModel(const Triple &TT,
switch (*CM) {
case CodeModel::Small:
- case CodeModel::Medium:
return *CM;
+ case CodeModel::Medium:
case CodeModel::Large:
if (!TT.isArch64Bit())
- report_fatal_error("Large code model requires LA64");
+ report_fatal_error("Medium/Large code model requires LA64");
return *CM;
default:
report_fatal_error(
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
index cee6dad1f095e1..0692cb92b69440 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
@@ -47,6 +47,7 @@ enum {
MO_IE_PC64_HI,
MO_LD_PC_HI,
MO_GD_PC_HI,
+ MO_CALL36
// TODO: Add more flags.
};
} // end namespace LoongArchII
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
index fe19a4f2d3c864..1dec816f347339 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
@@ -90,6 +90,8 @@ unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_LARCH_TLS_LE64_LO20;
case LoongArch::fixup_loongarch_tls_le64_hi12:
return ELF::R_LARCH_TLS_LE64_HI12;
+ case LoongArch::fixup_loongarch_call36:
+ return ELF::R_LARCH_CALL36;
// TODO: Handle more fixup-kinds.
}
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
index 178fa6e5262be3..78f74f58156a18 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
@@ -108,7 +108,11 @@ enum Fixups {
// 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
fixup_loongarch_tls_gd_hi20,
// Generate an R_LARCH_RELAX which indicates the linker may relax here.
- fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX
+ fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX,
+
+ // 36-bit fixup corresponding to %call36(foo) for a pair instructions:
+ // pcaddu18i+jirl.
+ fixup_loongarch_call36 = FirstLiteralRelocationKind + ELF::R_LARCH_CALL36
};
} // end namespace LoongArch
} // end namespace llvm
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
index d2ea062dc09a74..9ac0128f251728 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
@@ -241,6 +241,9 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
case LoongArchMCExpr::VK_LoongArch_TLS_GD_HI20:
FixupKind = LoongArch::fixup_loongarch_tls_gd_hi20;
break;
+ case LoongArchMCExpr::VK_LoongArch_CALL36:
+ FixupKind = LoongArch::fixup_loongarch_call36;
+ break;
}
} else if (Kind == MCExpr::SymbolRef &&
cast<MCSymbolRefExpr>(Expr)->getKind() ==
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
index 82c992b1cc8c4e..8ca8876a19b936 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
@@ -138,6 +138,8 @@ StringRef LoongArchMCExpr::getVariantKindName(VariantKind Kind) {
return "gd_pc_hi20";
case VK_LoongArch_TLS_GD_HI20:
return "gd_hi20";
+ case VK_LoongArch_CALL36:
+ return "call36";
}
}
@@ -180,6 +182,7 @@ LoongArchMCExpr::getVariantKindForName(StringRef name) {
.Case("ld_hi20", VK_LoongArch_TLS_LD_HI20)
.Case("gd_pc_hi20", VK_LoongArch_TLS_GD_PC_HI20)
.Case("gd_hi20", VK_LoongArch_TLS_GD_HI20)
+ .Case("call36", VK_LoongArch_CALL36)
.Default(VK_LoongArch_Invalid);
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
index 93251f8241033b..bd828116d7fa46 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
@@ -61,6 +61,7 @@ class LoongArchMCExpr : public MCTargetExpr {
VK_LoongArch_TLS_LD_HI20,
VK_LoongArch_TLS_GD_PC_HI20,
VK_LoongArch_TLS_GD_HI20,
+ VK_LoongArch_CALL36,
VK_LoongArch_Invalid // Must be the last item.
};
diff --git a/llvm/test/CodeGen/LoongArch/code-models.ll b/llvm/test/CodeGen/LoongArch/code-models.ll
index c610f645a06aeb..f93c316709284b 100644
--- a/llvm/test/CodeGen/LoongArch/code-models.ll
+++ b/llvm/test/CodeGen/LoongArch/code-models.ll
@@ -23,8 +23,8 @@ define i32 @call_globaladdress(i32 %a) nounwind {
; MEDIUM: # %bb.0:
; MEDIUM-NEXT: addi.d $sp, $sp, -16
; MEDIUM-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; MEDIUM-NEXT: pcalau12i $ra, %pc_hi20(callee)
-; MEDIUM-NEXT: jirl $ra, $ra, %pc_lo12(callee)
+; MEDIUM-NEXT: pcaddu18i $ra, %call36(callee)
+; MEDIUM-NEXT: jirl $ra, $ra, 0
; MEDIUM-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; MEDIUM-NEXT: addi.d $sp, $sp, 16
; MEDIUM-NEXT: ret
@@ -33,11 +33,11 @@ define i32 @call_globaladdress(i32 %a) nounwind {
; LARGE: # %bb.0:
; LARGE-NEXT: addi.d $sp, $sp, -16
; LARGE-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LARGE-NEXT: pcalau12i $a1, %got_pc_hi20(callee)
-; LARGE-NEXT: addi.d $ra, $zero, %got_pc_lo12(callee)
-; LARGE-NEXT: lu32i.d $ra, %got64_pc_lo20(callee)
-; LARGE-NEXT: lu52i.d $ra, $ra, %got64_pc_hi12(callee)
-; LARGE-NEXT: ldx.d $ra, $ra, $a1
+; LARGE-NEXT: pcalau12i $ra, %got_pc_hi20(callee)
+; LARGE-NEXT: addi.d $t8, $zero, %got_pc_lo12(callee)
+; LARGE-NEXT: lu32i.d $t8, %got64_pc_lo20(callee)
+; LARGE-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(callee)
+; LARGE-NEXT: ldx.d $ra, $t8, $ra
; LARGE-NEXT: jirl $ra, $ra, 0
; LARGE-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LARGE-NEXT: addi.d $sp, $sp, 16
@@ -68,8 +68,8 @@ define void @call_external_sym(ptr %dst) {
; MEDIUM-NEXT: .cfi_offset 1, -8
; MEDIUM-NEXT: ori $a2, $zero, 1000
; MEDIUM-NEXT: move $a1, $zero
-; MEDIUM-NEXT: pcalau12i $ra, %pc_hi20(memset)
-; MEDIUM-NEXT: jirl $ra, $ra, %pc_lo12(memset)
+; MEDIUM-NEXT: pcaddu18i $ra, %call36(memset)
+; MEDIUM-NEXT: jirl $ra, $ra, 0
; MEDIUM-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; MEDIUM-NEXT: addi.d $sp, $sp, 16
; MEDIUM-NEXT: ret
@@ -82,11 +82,11 @@ define void @call_external_sym(ptr %dst) {
; LARGE-NEXT: .cfi_offset 1, -8
; LARGE-NEXT: ori $a2, $zero, 1000
; LARGE-NEXT: move $a1, $zero
-; LARGE-NEXT: pcalau12i $a3, %pc_hi20(memset)
-; LARGE-NEXT: addi.d $ra, $zero, %pc_lo12(memset)
-; LARGE-NEXT: lu32i.d $ra, %pc64_lo20(memset)
-; LARGE-NEXT: lu52i.d $ra, $ra, %pc64_hi12(memset)
-; LARGE-NEXT: add.d $ra, $ra, $a3
+; LARGE-NEXT: pcalau12i $ra, %pc_hi20(memset)
+; LARGE-NEXT: addi.d $t8, $zero, %pc_lo12(memset)
+; LARGE-NEXT: lu32i.d $t8, %pc64_lo20(memset)
+; LARGE-NEXT: lu52i.d $t8, $t8, %pc64_hi12(memset)
+; LARGE-NEXT: add.d $ra, $t8, $ra
; LARGE-NEXT: jirl $ra, $ra, 0
; LARGE-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LARGE-NEXT: addi.d $sp, $sp, 16
@@ -105,17 +105,17 @@ define i32 @caller_tail(i32 %i) nounwind {
;
; MEDIUM-LABEL: caller_tail:
; MEDIUM: # %bb.0: # %entry
-; MEDIUM-NEXT: pcalau12i $a1, %pc_hi20(callee_tail)
-; MEDIUM-NEXT: jirl $zero, $a1, %pc_lo12(callee_tail)
+; MEDIUM-NEXT: pcaddu18i $t8, %call36(callee_tail)
+; MEDIUM-NEXT: jr $t8
;
; LARGE-LABEL: caller_tail:
; LARGE: # %bb.0: # %entry
-; LARGE-NEXT: pcalau12i $a1, %got_pc_hi20(callee_tail)
-; LARGE-NEXT: addi.d $a2, $zero, %got_pc_lo12(callee_tail)
-; LARGE-NEXT: lu32i.d $a2, %got64_pc_lo20(callee_tail)
-; LARGE-NEXT: lu52i.d $a2, $a2, %got64_pc_hi12(callee_tail)
-; LARGE-NEXT: ldx.d $a1, $a2, $a1
-; LARGE-NEXT: jr $a1
+; LARGE-NEXT: pcalau12i $t7, %got_pc_hi20(callee_tail)
+; LARGE-NEXT: addi.d $t8, $zero, %got_pc_lo12(callee_tail)
+; LARGE-NEXT: lu32i.d $t8, %got64_pc_lo20(callee_tail)
+; LARGE-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(callee_tail)
+; LARGE-NEXT: ldx.d $t7, $t8, $t7
+; LARGE-NEXT: jr $t7
entry:
%r = tail call i32 @callee_tail(i32 %i)
ret i32 %r
diff --git a/llvm/test/CodeGen/LoongArch/expand-call.ll b/llvm/test/CodeGen/LoongArch/expand-call.ll
index 86bf4292665b72..e0d179f92de682 100644
--- a/llvm/test/CodeGen/LoongArch/expand-call.ll
+++ b/llvm/test/CodeGen/LoongArch/expand-call.ll
@@ -1,6 +1,6 @@
; RUN: llc --mtriple=loongarch64 --stop-before loongarch-prera-expand-pseudo \
; RUN: --verify-machineinstrs < %s | FileCheck %s --check-prefix=NOEXPAND
-; RUN: llc --mtriple=loongarch64 --stop-after loongarch-prera-expand-pseudo \
+; RUN: llc --mtriple=loongarch64 --stop-before machine-opt-remark-emitter \
; RUN: --verify-machineinstrs < %s | FileCheck %s --check-prefix=EXPAND
declare void @callee()
diff --git a/llvm/test/CodeGen/LoongArch/global-address.ll b/llvm/test/CodeGen/LoongArch/global-address.ll
index a8f0ef648aa7c4..b8fa8d6a8d50ca 100644
--- a/llvm/test/CodeGen/LoongArch/global-address.ll
+++ b/llvm/test/CodeGen/LoongArch/global-address.ll
@@ -5,6 +5,10 @@
; RUN: llc --mtriple=loongarch64 --relocation-model=pic < %s | FileCheck %s --check-prefix=LA64PIC
; RUN: llc --mtriple=loongarch64 --code-model=large --relocation-model=static < %s | FileCheck %s --check-prefix=LA64LARGENOPIC
; RUN: llc --mtriple=loongarch64 --code-model=large --relocation-model=pic < %s | FileCheck %s --check-prefix=LA64LARGEPIC
+; RUN: llc --mtriple=loongarch64 --code-model=large --relocation-model=static \
+; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=LA64LARGENOPIC
+; RUN: llc --mtriple=loongarch64 --code-model=large --relocation-model=pic \
+; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=LA64LARGEPIC
@g = dso_local global i32 zeroinitializer, align 4
@G = global i32 zeroinitializer, align 4
@@ -53,32 +57,32 @@ define void @foo() nounwind {
; LA64LARGENOPIC-LABEL: foo:
; LA64LARGENOPIC: # %bb.0:
; LA64LARGENOPIC-NEXT: pcalau12i $a0, %got_pc_hi20(G)
-; LA64LARGENOPIC-NEXT: addi.d $a1, $zero, %got_pc_lo12(G)
-; LA64LARGENOPIC-NEXT: lu32i.d $a1, %got64_pc_lo20(G)
-; LA64LARGENOPIC-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(G)
-; LA64LARGENOPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGENOPIC-NEXT: addi.d $t8, $zero, %got_pc_lo12(G)
+; LA64LARGENOPIC-NEXT: lu32i.d $t8, %got64_pc_lo20(G)
+; LA64LARGENOPIC-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(G)
+; LA64LARGENOPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGENOPIC-NEXT: ld.w $a0, $a0, 0
; LA64LARGENOPIC-NEXT: pcalau12i $a0, %pc_hi20(g)
-; LA64LARGENOPIC-NEXT: addi.d $a1, $zero, %pc_lo12(g)
-; LA64LARGENOPIC-NEXT: lu32i.d $a1, %pc64_lo20(g)
-; LA64LARGENOPIC-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g)
-; LA64LARGENOPIC-NEXT: add.d $a0, $a1, $a0
+; LA64LARGENOPIC-NEXT: addi.d $t8, $zero, %pc_lo12(g)
+; LA64LARGENOPIC-NEXT: lu32i.d $t8, %pc64_lo20(g)
+; LA64LARGENOPIC-NEXT: lu52i.d $t8, $t8, %pc64_hi12(g)
+; LA64LARGENOPIC-NEXT: add.d $a0, $t8, $a0
; LA64LARGENOPIC-NEXT: ld.w $a0, $a0, 0
; LA64LARGENOPIC-NEXT: ret
;
; LA64LARGEPIC-LABEL: foo:
; LA64LARGEPIC: # %bb.0:
; LA64LARGEPIC-NEXT: pcalau12i $a0, %got_pc_hi20(G)
-; LA64LARGEPIC-NEXT: addi.d $a1, $zero, %got_pc_lo12(G)
-; LA64LARGEPIC-NEXT: lu32i.d $a1, %got64_pc_lo20(G)
-; LA64LARGEPIC-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(G)
-; LA64LARGEPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %got_pc_lo12(G)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %got64_pc_lo20(G)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(G)
+; LA64LARGEPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGEPIC-NEXT: ld.w $a0, $a0, 0
; LA64LARGEPIC-NEXT: pcalau12i $a0, %pc_hi20(.Lg$local)
-; LA64LARGEPIC-NEXT: addi.d $a1, $zero, %pc_lo12(.Lg$local)
-; LA64LARGEPIC-NEXT: lu32i.d $a1, %pc64_lo20(.Lg$local)
-; LA64LARGEPIC-NEXT: lu52i.d $a1, $a1, %pc64_hi12(.Lg$local)
-; LA64LARGEPIC-NEXT: add.d $a0, $a1, $a0
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %pc_lo12(.Lg$local)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %pc64_lo20(.Lg$local)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %pc64_hi12(.Lg$local)
+; LA64LARGEPIC-NEXT: add.d $a0, $t8, $a0
; LA64LARGEPIC-NEXT: ld.w $a0, $a0, 0
; LA64LARGEPIC-NEXT: ret
%V = load volatile i32, ptr @G
diff --git a/llvm/test/CodeGen/LoongArch/tls-models.ll b/llvm/test/CodeGen/LoongArch/tls-models.ll
index a2a3792a6a54be..3994df1da7163f 100644
--- a/llvm/test/CodeGen/LoongArch/tls-models.ll
+++ b/llvm/test/CodeGen/LoongArch/tls-models.ll
@@ -45,15 +45,15 @@ define ptr @f1() nounwind {
; LA64LARGEPIC-NEXT: addi.d $sp, $sp, -16
; LA64LARGEPIC-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64LARGEPIC-NEXT: pcalau12i $a0, %gd_pc_hi20(unspecified)
-; LA64LARGEPIC-NEXT: addi.d $a1, $zero, %got_pc_lo12(unspecified)
-; LA64LARGEPIC-NEXT: lu32i.d $a1, %got64_pc_lo20(unspecified)
-; LA64LARGEPIC-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(unspecified)
-; LA64LARGEPIC-NEXT: add.d $a0, $a1, $a0
-; LA64LARGEPIC-NEXT: pcalau12i $a1, %pc_hi20(__tls_get_addr)
-; LA64LARGEPIC-NEXT: addi.d $ra, $zero, %pc_lo12(__tls_get_addr)
-; LA64LARGEPIC-NEXT: lu32i.d $ra, %pc64_lo20(__tls_get_addr)
-; LA64LARGEPIC-NEXT: lu52i.d $ra, $ra, %pc64_hi12(__tls_get_addr)
-; LA64LARGEPIC-NEXT: add.d $ra, $ra, $a1
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %got_pc_lo12(unspecified)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %got64_pc_lo20(unspecified)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(unspecified)
+; LA64LARGEPIC-NEXT: add.d $a0, $t8, $a0
+; LA64LARGEPIC-NEXT: pcalau12i $ra, %pc_hi20(__tls_get_addr)
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %pc_lo12(__tls_get_addr)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %pc64_lo20(__tls_get_addr)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %pc64_hi12(__tls_get_addr)
+; LA64LARGEPIC-NEXT: add.d $ra, $t8, $ra
; LA64LARGEPIC-NEXT: jirl $ra, $ra, 0
; LA64LARGEPIC-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64LARGEPIC-NEXT: addi.d $sp, $sp, 16
@@ -76,10 +76,10 @@ define ptr @f1() nounwind {
; LA64LARGENOPIC-LABEL: f1:
; LA64LARGENOPIC: # %bb.0: # %entry
; LA64LARGENOPIC-NEXT: pcalau12i $a0, %ie_pc_hi20(unspecified)
-; LA64LARGENOPIC-NEXT: addi.d $a1, $zero, %ie_pc_lo12(unspecified)
-; LA64LARGENOPIC-NEXT: lu32i.d $a1, %ie64_pc_lo20(unspecified)
-; LA64LARGENOPIC-NEXT: lu52i.d $a1, $a1, %ie64_pc_hi12(unspecified)
-; LA64LARGENOPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGENOPIC-NEXT: addi.d $t8, $zero, %ie_pc_lo12(unspecified)
+; LA64LARGENOPIC-NEXT: lu32i.d $t8, %ie64_pc_lo20(unspecified)
+; LA64LARGENOPIC-NEXT: lu52i.d $t8, $t8, %ie64_pc_hi12(unspecified)
+; LA64LARGENOPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGENOPIC-NEXT: add.d $a0, $a0, $tp
; LA64LARGENOPIC-NEXT: ret
entry:
@@ -116,15 +116,15 @@ define ptr @f2() nounwind {
; LA64LARGEPIC-NEXT: addi.d $sp, $sp, -16
; LA64LARGEPIC-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64LARGEPIC-NEXT: pcalau12i $a0, %ld_pc_hi20(ld)
-; LA64LARGEPIC-NEXT: addi.d $a1, $zero, %got_pc_lo12(ld)
-; LA64LARGEPIC-NEXT: lu32i.d $a1, %got64_pc_lo20(ld)
-; LA64LARGEPIC-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(ld)
-; LA64LARGEPIC-NEXT: add.d $a0, $a1, $a0
-; LA64LARGEPIC-NEXT: pcalau12i $a1, %pc_hi20(__tls_get_addr)
-; LA64LARGEPIC-NEXT: addi.d $ra, $zero, %pc_lo12(__tls_get_addr)
-; LA64LARGEPIC-NEXT: lu32i.d $ra, %pc64_lo20(__tls_get_addr)
-; LA64LARGEPIC-NEXT: lu52i.d $ra, $ra, %pc64_hi12(__tls_get_addr)
-; LA64LARGEPIC-NEXT: add.d $ra, $ra, $a1
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %got_pc_lo12(ld)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %got64_pc_lo20(ld)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %got64_pc_hi12(ld)
+; LA64LARGEPIC-NEXT: add.d $a0, $t8, $a0
+; LA64LARGEPIC-NEXT: pcalau12i $ra, %pc_hi20(__tls_get_addr)
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %pc_lo12(__tls_get_addr)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %pc64_lo20(__tls_get_addr)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %pc64_hi12(__tls_get_addr)
+; LA64LARGEPIC-NEXT: add.d $ra, $t8, $ra
; LA64LARGEPIC-NEXT: jirl $ra, $ra, 0
; LA64LARGEPIC-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64LARGEPIC-NEXT: addi.d $sp, $sp, 16
@@ -147,10 +147,10 @@ define ptr @f2() nounwind {
; LA64LARGENOPIC-LABEL: f2:
; LA64LARGENOPIC: # %bb.0: # %entry
; LA64LARGENOPIC-NEXT: pcalau12i $a0, %ie_pc_hi20(ld)
-; LA64LARGENOPIC-NEXT: addi.d $a1, $zero, %ie_pc_lo12(ld)
-; LA64LARGENOPIC-NEXT: lu32i.d $a1, %ie64_pc_lo20(ld)
-; LA64LARGENOPIC-NEXT: lu52i.d $a1, $a1, %ie64_pc_hi12(ld)
-; LA64LARGENOPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGENOPIC-NEXT: addi.d $t8, $zero, %ie_pc_lo12(ld)
+; LA64LARGENOPIC-NEXT: lu32i.d $t8, %ie64_pc_lo20(ld)
+; LA64LARGENOPIC-NEXT: lu52i.d $t8, $t8, %ie64_pc_hi12(ld)
+; LA64LARGENOPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGENOPIC-NEXT: add.d $a0, $a0, $tp
; LA64LARGENOPIC-NEXT: ret
entry:
@@ -177,10 +177,10 @@ define ptr @f3() nounwind {
; LA64LARGEPIC-LABEL: f3:
; LA64LARGEPIC: # %bb.0: # %entry
; LA64LARGEPIC-NEXT: pcalau12i $a0, %ie_pc_hi20(ie)
-; LA64LARGEPIC-NEXT: addi.d $a1, $zero, %ie_pc_lo12(ie)
-; LA64LARGEPIC-NEXT: lu32i.d $a1, %ie64_pc_lo20(ie)
-; LA64LARGEPIC-NEXT: lu52i.d $a1, $a1, %ie64_pc_hi12(ie)
-; LA64LARGEPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGEPIC-NEXT: addi.d $t8, $zero, %ie_pc_lo12(ie)
+; LA64LARGEPIC-NEXT: lu32i.d $t8, %ie64_pc_lo20(ie)
+; LA64LARGEPIC-NEXT: lu52i.d $t8, $t8, %ie64_pc_hi12(ie)
+; LA64LARGEPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGEPIC-NEXT: add.d $a0, $a0, $tp
; LA64LARGEPIC-NEXT: ret
;
@@ -201,10 +201,10 @@ define ptr @f3() nounwind {
; LA64LARGENOPIC-LABEL: f3:
; LA64LARGENOPIC: # %bb.0: # %entry
; LA64LARGENOPIC-NEXT: pcalau12i $a0, %ie_pc_hi20(ie)
-; LA64LARGENOPIC-NEXT: addi.d $a1, $zero, %ie_pc_lo12(ie)
-; LA64LARGENOPIC-NEXT: lu32i.d $a1, %ie64_pc_lo20(ie)
-; LA64LARGENOPIC-NEXT: lu52i.d $a1, $a1, %ie64_pc_hi12(ie)
-; LA64LARGENOPIC-NEXT: ldx.d $a0, $a1, $a0
+; LA64LARGENOPIC-NEXT: addi.d $t8, $zero, %ie_pc_lo12(ie)
+; LA64LARGENOPIC-NEXT: lu32i.d $t8, %ie64_pc_lo20(ie)
+; LA64LARGENOPIC-NEXT: lu52i.d $t8, $t8, %ie64_pc_hi12(ie)
+; LA64LARGENOPIC-NEXT: ldx.d $a0, $t8, $a0
; LA64LARGENOPIC-NEXT: add.d $a0, $a0, $tp
; LA64LARGENOPIC-NEXT: ret
entry:
diff --git a/llvm/test/MC/LoongArch/Basic/Integer/invalid64.s b/llvm/test/MC/LoongArch/Basic/Integer/invalid64.s
index acddca9432a698..1c1c658ad440f8 100644
--- a/llvm/test/MC/LoongArch/Basic/Integer/invalid64.s
+++ b/llvm/test/MC/LoongArch/Basic/Integer/invalid64.s
@@ -65,7 +65,7 @@ addu16i.d $a0, $a0, 32768
## simm20
pcaddu18i $a0, 0x80000
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-524288, 524287]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %call36) or an integer in the range [-524288, 524287]
## simm20_lu32id
lu32i.d $a0, 0x80000
diff --git a/llvm/test/MC/LoongArch/Macros/macros-call.s b/llvm/test/MC/LoongArch/Macros/macros-call.s
new file mode 100644
index 00000000000000..ccdf34562d4970
--- /dev/null
+++ b/llvm/test/MC/LoongArch/Macros/macros-call.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --triple=loongarch64 %s | FileCheck %s
+
+call36 sym_call
+# CHECK: pcaddu18i $ra, %call36(sym_call)
+# CHECK-NEXT: jirl $ra, $ra, 0
+
+tail36 $t0, sym_tail
+# CHECK: pcaddu18i $t0, %call36(sym_tail)
+# CHECK-NEXT: jr $t0
+
diff --git a/llvm/test/MC/LoongArch/Relocations/relocations.s b/llvm/test/MC/LoongArch/Relocations/relocations.s
index 042cc93470a1e5..bec71e10389333 100644
--- a/llvm/test/MC/LoongArch/Relocations/relocations.s
+++ b/llvm/test/MC/LoongArch/Relocations/relocations.s
@@ -218,3 +218,8 @@ lu12i.w $t1, %gd_hi20(foo)
# RELOC: R_LARCH_TLS_GD_HI20 foo 0x0
# INSTR: lu12i.w $t1, %gd_hi20(foo)
# FIXUP: fixup A - offset: 0, value: %gd_hi20(foo), kind: FK_NONE
+
+pcaddu18i $t1, %call36(foo)
+# RELOC: R_LARCH_CALL36 foo 0x0
+# INSTR: pcaddu18i $t1, %call36(foo)
+# FIXUP: fixup A - offset: 0, value: %call36(foo), kind: FK_NONE
More information about the llvm-commits
mailing list