[llvm] [RISCV] Initial ISel support for the experimental zacas extension (PR #67918)

[Wang Pengcheng via llvm-commits]

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@@ -728,6 +807,38 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
   return true;
 }
 
+static Register getGPRPairEvenReg(Register PairedReg) {
+  assert(PairedReg >= RISCV::X0_PD && PairedReg <= RISCV::X30_PD &&
+         "Invalid GPR pair");
+  return (PairedReg - RISCV::X0_PD) * 2 + RISCV::X0;
+}
+
+bool RISCVExpandAtomicPseudo::expandAMOCAS(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsPaired,
+    int Width, MachineBasicBlock::iterator &NextMBBI) {
+  MachineInstr &MI = *MBBI;
+  DebugLoc DL = MI.getDebugLoc();
+
+  Register DestReg = MI.getOperand(0).getReg();
+  if (IsPaired)
+    DestReg = getGPRPairEvenReg(DestReg);
+  Register AddrReg = MI.getOperand(1).getReg();
+  Register NewValReg = MI.getOperand(3).getReg();
+  if (IsPaired)
+    NewValReg = getGPRPairEvenReg(NewValReg);
+  AtomicOrdering Ordering =
+      static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
+
+  MachineInstr *NewMI =
+      BuildMI(MBB, MBBI, DL, TII->get(getAMOCASForRMW(Ordering, Width, STI)))
+          .addReg(DestReg, RegState::Define)
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wangpc-pp wrote:

Is there any later pass for RISCV target? Is `RISCVExpandAtomicPseudoInsts` the last pass in the pipeline, isn't it?

https://github.com/llvm/llvm-project/pull/67918