[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction (PR #76210)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 22 00:57:53 PST 2023
================
@@ -14,35 +14,67 @@
//===----------------------------------------------------------------------===//
// AMX instructions
-let Predicates = [HasAMXTILE, In64BitMode] in {
- let SchedRW = [WriteSystem] in {
+let SchedRW = [WriteSystem] in {
+ let Predicates = [HasAMXTILE, NoEGPR, In64BitMode] in {
let hasSideEffects = 1,
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
- def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
- "ldtilecfg\t$src",
- [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
+ def LDTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+ "ldtilecfg\t$src",
+ [(int_x86_ldtilecfg addr:$src)]>,
+ VEX, T8PS;
let hasSideEffects = 1 in
- def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
- "sttilecfg\t$src",
- [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
+ def STTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+ "sttilecfg\t$src",
+ [(int_x86_sttilecfg addr:$src)]>,
+ VEX, T8PD;
----------------
phoebewang wrote:
Keep the format unchanged if the code is unrelated. The same below.
https://github.com/llvm/llvm-project/pull/76210
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