[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction (PR #76210)

[Phoebe Wang via llvm-commits]

================
@@ -14,35 +14,67 @@
 //===----------------------------------------------------------------------===//
 // AMX instructions
 
-let Predicates = [HasAMXTILE, In64BitMode] in {
-  let SchedRW = [WriteSystem] in {
+let SchedRW = [WriteSystem] in {
+  let Predicates = [HasAMXTILE, NoEGPR, In64BitMode] in {
     let hasSideEffects = 1,
         Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
-    def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
-                       "ldtilecfg\t$src",
-                       [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
+    def LDTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                      "ldtilecfg\t$src",
+                      [(int_x86_ldtilecfg addr:$src)]>,
+                    VEX, T8PS;
     let hasSideEffects = 1 in
-    def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
-                       "sttilecfg\t$src",
-                       [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
+    def STTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                      "sttilecfg\t$src",
+                      [(int_x86_sttilecfg addr:$src)]>,
+                    VEX, T8PD;
     let mayLoad = 1 in
     def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
                       (ins sibmem:$src),
                       "tileloadd\t{$src, $dst|$dst, $src}", []>,
-                      VEX, T8XD;
+                    VEX, T8XD;
     let mayLoad = 1 in
     def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
                         (ins sibmem:$src),
                         "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
-                        VEX, T8PD;
-    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
-    def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
-                        "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
+                      VEX, T8PD;
     let mayStore = 1 in
     def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
                        (ins sibmem:$dst, TILE:$src),
                        "tilestored\t{$src, $dst|$dst, $src}", []>,
-                       VEX, T8XS;
+                      VEX, T8XS;
+  } // HasAMXTILE, NoEGPR
+  let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
+    let hasSideEffects = 1,
+        Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
+    def LDTILECFG_EVEX : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                           "ldtilecfg\t$src",
+                           [(int_x86_ldtilecfg addr:$src)]>,
+                         EVEX, NoCD8, T8PS;
----------------
phoebewang wrote:

It looks to me the EVEX promotion only has difference with `EVEX, NoCD8`. I think we can try to reuse with multiclass as much as possible, e.g.:

defm : AMX_TILE_COMMON<"">, VEX;
defm: AMX_TILE_COMMON<"_EVEX">, EVEX, NoCD8;

https://github.com/llvm/llvm-project/pull/76210