[llvm] [AArch64] Implement spill/fill of predicate pair register classes (PR #76068)

[Momchil Velikov via llvm-commits]

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@@ -2378,11 +2378,13 @@ let Predicates = [HasSVEorSME] in {
     def LDR_ZZXI   : Pseudo<(outs   ZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
     def LDR_ZZZXI  : Pseudo<(outs  ZZZ_b:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
     def LDR_ZZZZXI : Pseudo<(outs ZZZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+    def LDR_PPXI   : Pseudo<(outs PPR2:$pp), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
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momchil-velikov wrote:

These offsets are checked when replacing frame index with actual addressing mode, so we know we are in range. I would suggest changing all these to `simm9` in a separate patch, if only to not make someone wonder why did we use such strange constraints.

https://github.com/llvm/llvm-project/pull/76068