[llvm] [AArch64] Implement spill/fill of predicate pair register classes (PR #76068)

[Paul Walker via llvm-commits]

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@@ -3771,6 +3771,13 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
     MinOffset = -256;
     MaxOffset = 255;
     break;
+  case AArch64::LDR_PPXI:
+  case AArch64::STR_PPXI:
+    Scale = TypeSize::getScalable(2);
+    Width = TypeSize::getScalable(2 * 2);
+    MinOffset = -256;
+    MaxOffset = 255;
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paulwalker-arm wrote:

`MaxOffset` should be 254 to account for the extra offset required when the operation gets serialised into a sequence of single register `LDR/STR` instructions.

https://github.com/llvm/llvm-project/pull/76068