[llvm] [AArch64] Implement spill/fill of predicate pair register classes (PR #76068)
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 20 09:34:48 PST 2023
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@@ -2221,6 +2222,7 @@ unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
+ case AArch64::STR_PPXI:
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momchil-velikov wrote:
Actually, I think the changes are correct and perhaps LDR/STR_ZZXI/etc need to be added here as well.
The store takes a single register as operand (representing a register pair).
Perhaps, I'll be able to construct a test case showing how it makes a difference, say in MachineLICM or in StackSlotColoring.
https://github.com/llvm/llvm-project/pull/76068
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