[llvm] [AArch64] Implement spill/fill of predicate pair register classes (PR #76068)

[Momchil Velikov via llvm-commits]

================
@@ -2221,6 +2222,7 @@ unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case AArch64::STRDui:
   case AArch64::STRQui:
   case AArch64::STR_PXI:
+  case AArch64::STR_PPXI:
----------------
momchil-velikov wrote:

Hmm, very likely they are here by mistake. I'll retest and will probably remove these two changes.

https://github.com/llvm/llvm-project/pull/76068