[llvm] [RISCV][NFC] Refine MCOperandPredicate code for rtlist. (PR #76028)

[Yeting Kuo via llvm-commits]

https://github.com/yetingk created https://github.com/llvm/llvm-project/pull/76028

(Imm <= 15) could be implied by isUInt<4>(Imm).

>From bd92e512a00793856dcbd03c5923a75ea6f065bc Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Wed, 20 Dec 2023 00:33:32 -0800
Subject: [PATCH] [RISCV][NFC] Refine MCOperandPredicate code for rtlist.

(Imm <= 15) could be implied by isUInt<4>(Imm).
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZc.td | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a78f3624446871..9a7249fe3e3d6c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -56,9 +56,8 @@ def rlist : Operand<OtherVT> {
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    if (!isUInt<4>(Imm)) return false;
     // 0~3 Reserved for EABI
-    return (Imm >= 4) && (Imm <= 15);
+    return isUInt<4>(Imm) && Imm >= 4;
   }];
  }