[llvm] [RISCV][MISched] Set EnableIntervals to true for SiFive7 (PR #75681)

NAKAMURA Takumi via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 19 18:15:27 PST 2023

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chapuni wrote:

Does it fail in -Asserts?

https://github.com/llvm/llvm-project/pull/75681

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