[llvm] [RISCV][MISched] Set EnableIntervals to true for SiFive7 (PR #75681)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,56 @@
+# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler      \
+# RUN:  -debug-only=machine-scheduler -misched-dump-schedule-trace             \
+# RUN:  -misched-topdown -o - %s 2>&1 | FileCheck %s
+
+# The purpose of this test is to show that the VADD instructions are issued at
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michaelmaitland wrote:

`i` in the table below signifies the cycle that a VADD instruction `is issued at`. If we want to talk about multiple VADD instructions, then `i`s in the table below signify the cycles that the `VADD` instructions `are issued at`.

https://github.com/llvm/llvm-project/pull/75681