[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

It can be multiple lines. It should summarize the changes in this PR. Dont worry about squashing into one, that will happen when we click "Squash and Merge"

https://github.com/llvm/llvm-project/pull/71400