[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)

Jiahan Xie via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 15 10:09:18 PST 2023

Previous message: [llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)
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jiahanxie353 wrote:

> Can you please update PR description before commit?

Sure!

Should it be a one-line description?
And should I manually squash all commits into one?

https://github.com/llvm/llvm-project/pull/71400

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