[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)

[Jiahan Xie via llvm-commits]

jiahanxie353 wrote:

> It looks like CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll is failing.

That's weird because I just re-ran `llvm/utils/update_mir_test_checks.py --llc-binary=build/bin/llc  llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll` locally and it's fine

https://github.com/llvm/llvm-project/pull/71400