[llvm] [RISCV][GlobalISel] Represent RISC-V vector types using LLT scalable vectors; and legalize vectorized operations for G_ADD, G_SUB, G_AND, G_OR, and G_XOR opcodes (PR #71400)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 15 06:42:58 PST 2023


michaelmaitland wrote:

It looks like CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll is failing.

https://github.com/llvm/llvm-project/pull/71400


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