[llvm] [RISCV] Rematerialize load (PR #73924)

[Niwin Anto via llvm-commits]

================
@@ -626,7 +626,7 @@ def BGE  : BranchCC_rri<0b101, "bge">;
 def BLTU : BranchCC_rri<0b110, "bltu">;
 def BGEU : BranchCC_rri<0b111, "bgeu">;
 
-let IsSignExtendingOpW = 1 in {
+let IsSignExtendingOpW = 1, isReMaterializable = 1 in {
----------------
niwinanto wrote:

I tried to include `ld` as you suggested,
But `rv64-stackmap.ll` is failing with `error: ran out of registers during register allocation`.
Especially, testcase
```
 Spilled stack map values.
;
; Verify 28 stack map entries.
;
; CHECK-LABEL:  .word   .L{{.*}}-spilledValue
; CHECK-NEXT:   .half   0   
; CHECK-NEXT:   .half   28  
;
; Check that at least one is a spilled entry from RBP.
; Location: Indirect RBP + ... 
; CHECK:        .byte   3   
; CHECK-NEXT:   .byte   0   
; CHECK-NEXT:   .half   8   
; CHECK-NEXT:   .half   2   
; CHECK-NEXT:   .half   0   
; CHECK-NEXT:   .word
define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { 
entry:
  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 28, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
  ret void
}

declare void @llvm.experimental.stackmap(i64, i32, ...)
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
```
I would like to investigate bit more to understand what is going wrong.

https://github.com/llvm/llvm-project/pull/73924