[llvm] [AMDGPU][NFC] Test autogenerated llc tests for COV5 (PR #74339)
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Fri Dec 8 12:15:36 PST 2023
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git-clang-format --diff 8f6f5ec77615e2ae137d0b1e306abbac6f7fc0e8 a16ede8772381ec3e7500d0a8234198e283a22cf -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 7ac36d4b02..dd71a96173 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1343,15 +1343,15 @@ bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
SIInstrFlags::FlatGlobal));
if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
- // Assume the we will use FLAT for all global memory accesses
- // on VI.
- // FIXME: This assumption is currently wrong. On VI we still use
- // MUBUF instructions for the r + i addressing mode. As currently
- // implemented, the MUBUF instructions only work on buffer < 4GB.
- // It may be possible to support > 4GB buffers with MUBUF instructions,
- // by setting the stride value in the resource descriptor which would
- // increase the size limit to (stride * 4GB). However, this is risky,
- // because it has never been validated.
+ // Assume the we will use FLAT for all global memory accesses
+ // on VI.
+ // FIXME: This assumption is currently wrong. On VI we still use
+ // MUBUF instructions for the r + i addressing mode. As currently
+ // implemented, the MUBUF instructions only work on buffer < 4GB.
+ // It may be possible to support > 4GB buffers with MUBUF instructions,
+ // by setting the stride value in the resource descriptor which would
+ // increase the size limit to (stride * 4GB). However, this is risky,
+ // because it has never been validated.
return isLegalFlatAddressingMode(AM);
}
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https://github.com/llvm/llvm-project/pull/74339
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